Abstract: According to some example embodiments, a method includes receiving, a first command from a host device; determining, if the first command is part of an association group of commands by determining a first value of a first parameter of the first command in an association context table entry is greater than zero, the first parameter including a total number of commands in the association group of commands; determining, a first value of a second parameter of the first command, the second parameter including a tag value identifying the association group of commands; decrementing, the first value of the first parameter of the first command in the association context table entry; determining, if the first value of the first parameter in the association context table entry is zero; and executing, an action indicated in a third parameter of the first command.

Abstract: A method of low-latency direct data access to non-volatile flash memory in at least one NVMe-oF SSD device connected over Ethernet. The method includes transmitting, from a low-latency direct access (LL-DAX) block storage software layer at a host, a remote direct memory access (RDMA) write request to the flash memory. The RDMA write request includes data, a storage address, a length of a data transfer operation, and an operation code. The method also includes receiving, at the host, an RDMA level acknowledgement indicating that the data has been persisted to the flash memory. The method also includes transmitting, from the LL-DAX block storage software layer, an RDMA read request to the flash memory that includes a storage address, a length of a data transfer, and an operation code. The method also includes receiving, at the host, data packets from the flash memory corresponding to the RDMA read request.

Abstract: A system includes a host device; a storage device including an embedded processor; and a bridge kernel device including a bridge kernel hardware and a bridge kernel firmware, wherein the bridge kernel device is configured to receive a plurality of arguments from the host device and transfer the plurality of arguments to the embedded processor for data processing.

Abstract: A system and a method to detect malicious software written to an Ethernet solid-state drive (eSSD). The system includes an Ethernet switch, at least one SSD, and a baseboard management controller (BMC). The Ethernet switch receives write data from a communication network in response to a write command. The at least one SSD receives the write data from the Ethernet switch and stores the received write data. The BMC receives from the at least one SSD the received write data. The BMC determines whether the received write data contains malicious software. The received write data may be contained in a plurality of Ethernet packets in which case the BMC stores the received write data in a scan buffer in an order that is based on an assembled order of the received write data.

Abstract: A method includes: receiving, at an acceleration platform manager (APM) from an application service manager (ASM), application function processing information; allocating, by the APM, a first storage processing accelerator (SPA) from a plurality of SPAs, wherein at least one SPA of the plurality of SPAs comprises a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs comprising n SPEs, enabling the plurality of SPEs in the first SPA, wherein once enabled, the at least one SPE of the plurality of SPEs in the first SPA is configured to process data based on the application function processing information; determining, by the APM, if data processing is completed by the at least one SPE of the plurality of SPEs in the first SPA; and sending, by the APM, a result of the data processing by the SPEs of the first SPA, to the ASM.

Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive a memory access request, wherein the memory access request is associated with a data set. The apparatus may include a non-volatile memory storage circuit configured to create and store a transformed data set. The apparatus may include a translation circuit comprising at least one machine learning circuit. The translation circuit may be configured to: in response to a write memory access, convert an original version of the data set to the transformed data set, and in response to a read memory access, convert the transformed data set to a reconstructed data set.

Abstract: A chassis is disclosed. The chassis may include a processor, a switch, and at least one storage device in communication with a remote processor. The storage device may support an active power mode and a low power mode. A response to a Keep Alive (KA) message may be sent to the remote processor on behalf of the storage device when the storage device is in low power mode.

Abstract: A host machine is disclosed. The host machine may include a host processor, a memory, an operating system running on the host processor, and an application running under the operating system on the host processor. The host machine may also include a Peripheral Component Interconnect Express (PCIe) tunnel to a Non-Volatile Memory Express (NVMe) Solid State Drive (SSD) and an RPC capture module which may capture the RPC from the application and deliver a result of the RPC to the application as though from the host processor, where the NVMe SSD may execute the RPC to generate the result.

Abstract: A storage device is disclosed. The storage device may include storage to store data and a controller to manage reading data from and writing data to the storage. The controller may also include a receiver to receive a plurality of requests, information determination logic to determine information about the plurality of requests, storage for the information about a plurality of requests, and sharing logic to share the information with a management controller.

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction.

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream endpoint enables communication with the processor; two downstream root ports enable communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include two endpoints of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.

Abstract: A system and a method to detect malicious software written to an Ethernet solid-state drive (eSSD). The system includes an Ethernet switch, at least one SSD, and a baseboard management controller (BMC). The Ethernet switch receives write data from a communication network in response to a write command. The at least one SSD receives the write data from the Ethernet switch and stores the received write data. The BMC receives from the at least one SSD the received write data. The BMC determines whether the received write data contains malicious software. The received write data may be contained in a plurality of Ethernet packets in which case the BMC stores the received write data in a scan buffer in an order that is based on an assembled order of the received write data.

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a physical function (PF) to expose the storage device, a second function to expose the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction.

Abstract: A system and method for distributed erasure coding. A plurality of storage devices is directly connected to one or more host computers, without an intervening central controller distributing data to the storage devices and providing data protection. Parity codes are stored in one or more dedicated storage devices or distributed over a plurality of the storage devices. When a storage device receives a write command, it calculates a partial parity code, and, if the parity code for the data being written is on another storage device, sends the partial parity code to the other storage device, which updates the parity code using the partial parity code.

Abstract: A system and method for providing erasure code data protection for an array of solid state drives. The solid state drives are connected to an Ethernet switch which includes a RAID control circuit, or a state machine, to process read or write commands that may be received from a remote host. The RAID control circuit, if present, uses a low-latency cache to execute write commands, and the state machine, if present, uses a local central processing unit, which in turn uses a memory as a low-latency cache, to similar effect.

Abstract: A storage device is disclosed. The storage device may include storage to store data and a controller to manage reading data from and writing data to the storage. The controller may also include a receiver to receive a plurality of requests, information determination logic to determine information about the plurality of requests, storage for the information about a plurality of requests, and sharing logic to share the information with a management controller.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to facilitate communication of memory accesses, for a storage memory, between the apparatus and a host device. The apparatus may include a statistics monitor circuit configured to record, as the memory accesses occur, statistics regarding data associated with the memory accesses. The apparatus may include a memory interface circuit configured to communicate the memory accesses between the apparatus and at least one storage memory.