Patents by Inventor Ramdas P. Kachare

Ramdas P. Kachare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11204819
    Abstract: A system includes a host device; a storage device including an embedded processor; and a bridge kernel device including a bridge kernel hardware and a bridge kernel firmware, wherein the bridge kernel device is configured to receive a plurality of arguments from the host device and transfer the plurality of arguments to the embedded processor for data processing.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: December 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ramdas P. Kachare, Stephen G. Fischer, Oscar P. Pinto
  • Publication number: 20210377342
    Abstract: A method of transferring data to an end user via a content distribution network using an nonvolatile memory express over fabrics (NVMe-oF) device, the method including receiving a read request at the NVMe-oF device, translating a logical address corresponding to the data to a physical address, fetching the data from a flash storage of the NVMe-oF device, processing the data with a GPU that is either embedded in the NVMe-oF device, or on a same chassis as the NVMe-oF device, and transferring the data.
    Type: Application
    Filed: August 17, 2021
    Publication date: December 2, 2021
    Inventors: Harry Rogers, Sompong Paul Olarig, Ramdas P. Kachare
  • Patent number: 11169738
    Abstract: A system and method for providing erasure code data protection for an array of solid state drives. The solid state drives are connected to an Ethernet switch which includes a RAID control circuit, or a state machine, to process read or write commands that may be received from a remote host. The RAID control circuit, if present, uses a low-latency cache to execute write commands, and the state machine, if present, uses a local central processing unit, which in turn uses a memory as a low-latency cache, to similar effect.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: November 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sompong Paul Olarig, Vikas K. Sinha, Fred Worley, Ramdas P. Kachare, Stephen G. Fischer
  • Publication number: 20210318804
    Abstract: A storage device is disclosed. The storage device may include storage to store data and a controller to manage reading data from and writing data to the storage. The controller may also include a receiver to receive a plurality of requests, information determination logic to determine information about the plurality of requests, storage for the information about a plurality of requests, and sharing logic to share the information with a management controller.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Ramdas P. KACHARE, Sompong Paul OLARIG, Wentao WU
  • Publication number: 20210303156
    Abstract: A storage device is disclosed. The storage device may include storage for data. A host interface may receive a write request from a host at the storage device. The write request may include a data chunk and a data identifier (ID). A class ID determiner circuitry may determine a class ID for the data chunk. A mapping table may map the data ID to the class ID.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 30, 2021
    Inventors: Ramdas P. KACHARE, Manali SHARMA, Praveen KRISHNAMOORTHY
  • Publication number: 20210303498
    Abstract: A system is disclosed. The system may include a Solid State Drive (SSD) and a co-processor. The SSD may include storage for data, storage for a unique SSD identifier (ID), and storage for a unique co-processor ID. The co-processor include storage for the unique SSD ID, and storage for the unique co-processor ID. A hardware interface may permit communication between the SSD and the co-processor.
    Type: Application
    Filed: April 14, 2021
    Publication date: September 30, 2021
    Inventors: Oscar P. PINTO, Ramdas P. KACHARE
  • Patent number: 11132310
    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 28, 2021
    Inventors: Ramdas P. Kachare, Fred Worley, Harry Rogers, Wentao Wu, Nagarajan Subramaniyan
  • Publication number: 20210294761
    Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Inventors: Ramdas P. KACHARE, Zvi GUZ, Son T. PHAM, Anahita SHAYESTEH, Xuebin YAO, Oscar Prem PINTO
  • Publication number: 20210294699
    Abstract: A system and method for providing erasure code protection across multiple storage devices. A data switch in a storage system connects a plurality of storage devices to a remote host. Each storage device is also connected to a controller, e.g., a baseboard management controller. During normal operation, read and write commands from the remote host are sent to respective storage devices through the data switch. When a write command is executed, the storage device executing the command sends a copy of the data to the controller, which generates and stores erasure codes, e.g., on a storage device that is dedicated to the storage of erasure codes, and invisible to the remote host. When a device fails or is removed, the controller reconfigures the data switch to redirect all traffic addressed to the failed or absent storage device to the controller, and the controller responds to host commands in its stead.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Sompong Paul Olarig, David Schwaderer, Ramdas P. Kachare
  • Publication number: 20210294494
    Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 23, 2021
    Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz
  • Publication number: 20210281639
    Abstract: A method may include transferring data between a host and a first storage device through a first storage interface, transferring data between the host and a second storage device through a second storage interface, and transferring data between the first storage device and the second storage device through a peer-to-peer channel. A storage system may include a host interface, a first storage device having a first storage interface coupled to the host interface, a second storage device having a second storage interface coupled to the host interface, and a peer-to-peer bus coupled between the first and second storage devices. A storage device may include a storage medium, a storage device controller coupled to the storage medium, a storage interface coupled to the storage device controller, and a peer-to-peer interface coupled to the storage device controller.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 9, 2021
    Inventors: Ramdas P. KACHARE, Sompong Paul OLARIG, Matthew Shaun BRYSON
  • Patent number: 11112972
    Abstract: A method includes: receiving, at an acceleration platform manager (APM) from an application service manager (ASM), application function processing information; allocating, by the APM, a first storage processing accelerator (SPA) from a plurality of SPAs, wherein at least one SPA of the plurality of SPAs comprises a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs comprising n SPEs, enabling the plurality of SPEs in the first SPA, wherein once enabled, the at least one SPE of the plurality of SPEs in the first SPA is configured to process data based on the application function processing information; determining, by the APM, if data processing is completed by the at least one SPE of the plurality of SPEs in the first SPA; and sending, by the APM, a result of the data processing by the SPEs of the first SPA, to the ASM.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz
  • Publication number: 20210263762
    Abstract: A storage device is disclosed. The storage device may include at least one controller for a virtual machine (VM) that is on a source host. Storage in the storage device may store data for the VM. A second storage may store a storage state for the VM. A storage device controller may process at least one read request received from the controller for the VM using the first storage and at least one write request received from the controller for the VM using the first storage. A VM migration state monitor and capture module may assist in the migration of the VM from the source host to a destination host.
    Type: Application
    Filed: August 28, 2020
    Publication date: August 26, 2021
    Inventors: Ramdas P. KACHARE, Oscar P. PINTO, Yang seok KI
  • Patent number: 11100017
    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 24, 2021
    Inventors: Ramdas P. Kachare, Fred Worley, Harry Rogers, Wentao Wu, Nagarajan Subramaniyan
  • Patent number: 11102294
    Abstract: A method of transferring data to an end user via a content distribution network using an nonvolatile memory express over fabrics (NVMe-oF) device, the method including receiving a read request at the NVMe-oF device, translating a logical address corresponding to the data to a physical address, fetching the data from a flash storage of the NVMe-oF device, processing the data with a GPU that is either embedded in the NVMe-oF device, or on a same chassis as the NVMe-oF device, and transferring the data.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 24, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Harry Rogers, Sompong Paul Olarig, Ramdas P. Kachare
  • Publication number: 20210247935
    Abstract: A multiple function storage device is disclosed. The multiple function storage device may include an enclosure, a storage device associated with the enclosure, and an bridging device associated with the enclosure. The storage device may include a connector to receive a first message using a first protocol originating at a host, a physical function (PF) and a virtual function (VF) exposed by the storage device via the connector, storage for data relating to the first message, and a controller to manage writing a write data to the storage and reading a read data from the storage.
    Type: Application
    Filed: November 25, 2020
    Publication date: August 12, 2021
    Inventors: Amir BEYGI, Jimmy LAU, Ramdas P. KACHARE
  • Publication number: 20210240245
    Abstract: A system is disclosed that provides emergency backup power to a solid-state drive (SSD) that may not contain any internal supercapacitors. The SSD may include a first connector and a hold-up power supply. The first connector may have a predetermined form factor and may being capable of being connected to a corresponding connector of a midplane of a storage system. The first connector may include a main power connection that is connected to a main power supply of the midplane if the first connector is connected to the corresponding connector of the midplane. The hold-up power supply may be internal to the SSD, and may receive hold-up energy from an external energy source for a predetermined amount of time after the first connector has been disconnected from the main power connection of the midplane so that the SSD may store any host data write requests that the SSD has acknowledged.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Inventors: Sompong Paul OLARIG, Ramdas P. KACHARE, Wentao WU
  • Publication number: 20210232198
    Abstract: A storage system comprises one or more storage devices, power supplies supplying power to the storage device, a processor that performs in response to determining that the total power consumption of the one or more storage devices is less than a first percentage threshold of a load of the active power supplies, deactivating one or more of the active power supplies until the total power consumption is equal to or greater than the first percentage threshold of a load of each of the active power supplies, and in response to determining that the total power consumption is equal to or greater than a second percentage threshold of a load of each of the active power supplies, activating one or more of the deactivated ones of the power supplies until the total power consumption is less than the second percentage threshold of the load of each of the active power supplies.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: Ramdas P. Kachare, Wentao Wu, Sompong Paul Olarig
  • Patent number: 11073987
    Abstract: A storage device is disclosed. The storage device may include storage to store data and a controller to manage reading data from and writing data to the storage. The controller may also include a receiver to receive a plurality of requests, information determination logic to determine information about the plurality of requests, storage for the information about a plurality of requests, and sharing logic to share the information with a management controller.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 27, 2021
    Inventors: Ramdas P. Kachare, Sompong Paul Olarig, Wentao Wu
  • Patent number: 11061574
    Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz