Patents by Inventor Ramin Farjad
Ramin Farjad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120069938Abstract: A serial communication system includes a receiver with an amplitude monitor. The amplitude monitor compares the input signal with a reference level in response to a sample clock. The sample clock is periodically phase shifted with respect to the incoming data so the amplitude monitor is sure to sample an incoming data eye at or near the peak amplitude over a selected sample period. The amplitude detector notes the detection of an input signal if the input signal surpasses the reference level for any sample phase. The amplitude monitor experiments with different sample-clock phases over a number of data symbols, but is capable of measuring amplitude fast enough to resolve amplitude-based signals used for rate negotiation.Type: ApplicationFiled: November 14, 2011Publication date: March 22, 2012Applicant: RAMBUS INC.Inventor: Ramin Farjad-Rad
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Publication number: 20120044984Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.Type: ApplicationFiled: October 28, 2011Publication date: February 23, 2012Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian Leibowitz
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Patent number: 8085880Abstract: A serial communication system includes a receiver that incorporates an amplitude monitor, which may be used to set and maintain appropriate termination-resistance values and transmit pre-emphasis and receive equalization settings. The amplitude monitor can note the presence or absence of input signals, as is required by some communication standards, such as those that require support for “out-of-band” (OOB) signaling for e.g. rate negotiation. The amplitude monitor compares the input signal with a reference level in response to a sample clock. The sample clock is periodically phase shifted with respect to the incoming data so the amplitude monitor is sure to sample an incoming data eye at or near the peak amplitude over a selected sample period. The amplitude detector notes the detection of an input signal if the input signal surpasses the reference level for any sample phase.Type: GrantFiled: December 23, 2004Date of Patent: December 27, 2011Assignee: RAMBUS Inc.Inventor: Ramin Farjad-rad
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Publication number: 20110310949Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.Type: ApplicationFiled: August 23, 2011Publication date: December 22, 2011Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian Leibowitz
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Publication number: 20110305271Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.Type: ApplicationFiled: August 23, 2011Publication date: December 15, 2011Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian Leibowitz
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Patent number: 7844023Abstract: A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system comprises at least two phase detectors coupled to the multi-phase clock generator for receiving component clock signals of the multi-phase clock generator, wherein at least some of the component clock signals are offset from each other in phase. Each of the phase detectors detects phase differences between pairs of component clock signals. The system includes a summer coupled to the at least two phase detectors for measuring the phase differences between the at least two phase detectors. The system includes at least one variable delay element for receiving the measured phase difference and for providing a delay which is proportional to an output value of the summer. The delay is used to reduce the phase differences.Type: GrantFiled: October 15, 2008Date of Patent: November 30, 2010Assignee: Rambus Inc.Inventor: Ramin Farjad-Rad
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Patent number: 7786816Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.Type: GrantFiled: July 28, 2008Date of Patent: August 31, 2010Assignee: Rambus Inc.Inventors: William J. Dally, Ramin Farjad-Rad, John W. Poulton, Thomas H. Greer, III, Hiok-Tiaq Ng, Teva J. Stone
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Patent number: 7683680Abstract: A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be fed back to control the phase of one of the timing signals. The phase comparator and charge pump circuit can be included in a multiplier circuitry in which the phase of an input signal is directly compared to the phase of an edge of the multiplied signal.Type: GrantFiled: August 30, 2005Date of Patent: March 23, 2010Assignee: Rambus, Inc.Inventors: William J. Dally, Ramin Farjad-Rad, Teva J. Stone, Xiaoying Yu, John W. Poulton
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Publication number: 20100054323Abstract: An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measures of eye amplitude to the adaptive control logic. The control logic experiments with different equalization settings while monitoring the resulting eye amplitude to find the equalization setting that provides incoming data eyes of the highest amplitude. A data filter may be included to enable the amplitude detector only in response to particular incoming data patterns.Type: ApplicationFiled: November 10, 2009Publication date: March 4, 2010Applicant: Rambus Inc.Inventor: Ramin Farjad-rad
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Publication number: 20100046597Abstract: An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measures of eye amplitude to the adaptive control logic. The control logic experiments with different equalization settings while monitoring the resulting eye amplitude to find the equalization setting that provides incoming data eyes of the highest amplitude. A data filter may be included to enable the amplitude detector only in response to particular incoming data patterns.Type: ApplicationFiled: August 19, 2009Publication date: February 25, 2010Applicant: Rambus Inc.Inventor: Ramin Farjad-rad
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Patent number: 7639736Abstract: An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measures of eye amplitude to the adaptive control logic. The control logic experiments with different equalization settings while monitoring the resulting eye amplitude to find the equalization setting that provides incoming data eyes of the highest amplitude. A data filter may be included to enable the amplitude detector only in response to particular incoming data patterns.Type: GrantFiled: September 10, 2004Date of Patent: December 29, 2009Assignee: Rambus Inc.Inventor: Ramin Farjad-rad
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Publication number: 20090097605Abstract: A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system comprises at least two phase detectors coupled to the multi-phase clock generator for receiving component clock signals of the multi-phase clock generator, wherein at least some of the component clock signals are offset from each other in phase. Each of the phase detectors detects phase differences between pairs of component clock signals. The system includes a summer coupled to the at least two phase detectors for measuring the phase differences between the at least two phase detectors. The system includes at least one variable delay element for receiving the measured phase difference and for providing a delay which is proportional to an output value of the summer. The delay is used to reduce the phase differences.Type: ApplicationFiled: October 15, 2008Publication date: April 16, 2009Applicant: RAMBUSInventor: RAMIN FARJAD-RAD
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Publication number: 20090015340Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.Type: ApplicationFiled: July 28, 2008Publication date: January 15, 2009Applicant: Rambus Inc.Inventors: William J. Dally, Ramin Farjad-Rad, John W. Poulton, Thomas H. Greer, III, Hiok-Tiaq Ng, Teva J. Stone
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Patent number: 7443941Abstract: A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system comprises at least two phase detectors coupled to the multi-phase clock generator for receiving component clock signals of the multi-phase clock generator, wherein at least some of the component clock signals are offset from each other in phase. Each of the phase detectors detects phase differences between pairs of component clock signals. The system includes a summer coupled to the at least two phase detectors for measuring the phase differences between the at least two phase detectors. The system includes at least one variable delay element for receiving the measured phase difference and for providing a delay which is proportional to an output value of the summer. The delay is used to reduce the phase differences.Type: GrantFiled: January 22, 2004Date of Patent: October 28, 2008Assignee: Rambus Inc.Inventor: Ramin Farjad-rad
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Patent number: 7414489Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.Type: GrantFiled: May 25, 2006Date of Patent: August 19, 2008Assignee: Rambus Inc.Inventors: William J. Dally, Ramin Farjad-Rad, John W. Poulton, Thomas H. Greer, III, Hiok-Tiaq Ng, Teva J. Stone
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Publication number: 20080094109Abstract: A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.Type: ApplicationFiled: December 21, 2007Publication date: April 24, 2008Inventors: Ramin Farjad-rad, John Poulton, John Eble, Thomas Greer, Robert Palmer
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Patent number: 7333578Abstract: An input data sequence is sampled according to a sampling clock such that a first set of samples corresponds to data values and a second set of samples corresponds to edges between the data values. The phase error between data transitions in the input sequence and the sampled edges is determined based on amplitudes of the sampled edges. The sampling clock's phase is adjusted based on the determined phase error. Typically, the phase error is proportional to an amplitude of a sampled edge. Sampled edge amplitude values are added or subtracted, according to the direction of each transition about each edge to form an error value which indicates the amount phase error.Type: GrantFiled: May 22, 2001Date of Patent: February 19, 2008Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Ramin Farjad-Rad, Mark Horowitz
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Patent number: 7319345Abstract: A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.Type: GrantFiled: December 1, 2004Date of Patent: January 15, 2008Assignee: Rambus Inc.Inventors: Ramin Farjad-rad, John W. Poulton, John Eble, Thomas H. Greer, III, Robert Palmer
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Publication number: 20070263757Abstract: A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.Type: ApplicationFiled: July 18, 2007Publication date: November 15, 2007Inventors: William Dally, John Edmondson, Ramin Farjad-Rad
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Patent number: 7274242Abstract: A tracking switch includes an MOS switching transistor with a control terminal coupled to a CMOS inverter. The relative geometries of the transistors that make up the inverter are significantly imbalanced, resulting is substantially different drive strengths (i.e., substantially different on-resistances). The gate of the switching transistor exhibits parasitic capacitances between its current-handling terminals and its control terminal. When the switching transistor is on, these capacitances shunt a portion of the switched signal to a power-supply node, with the problem increasing with the frequency of the propagated signal. The geometry of the transistor used to turn on the switching transistor is selected to produce a high on-resistance, which introduces a high-impedance path from the control terminal of the switching transistor to ground when the switch is closed.Type: GrantFiled: November 2, 2004Date of Patent: September 25, 2007Assignee: Rambus Inc.Inventor: Ramin Farjad-rad