Patents by Inventor Ramin Ghodsi

Ramin Ghodsi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145370
    Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Feng Pan, Jaekwan Park, Ramin Ghodsi
  • Publication number: 20210304829
    Abstract: Memories might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to determine a particular voltage level applied to each of the access lines that is deemed to activate each memory cell of a first subset of the strings of series-connected memory cells programmed to store respective data states that are each lower than or equal to a first data state of a plurality of data states, apply the particular voltage level to a particular access line of the plurality of access lines, and for each memory cell connected to the particular access line that is contained in a second subset of the strings of series-connected memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tommaso Vali, Ramin Ghodsi
  • Patent number: 11107536
    Abstract: Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
  • Patent number: 11056201
    Abstract: Memory might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to increase a voltage level applied to each of the access lines, determine a particular voltage level at which each memory cell of a first set of strings of memory cells is deemed to be activated while increasing the voltage level applied to the access lines, decrease the voltage level applied to a particular access line without decreasing the voltage level applied to each remaining access line, and, for each memory cell connected to the particular access line and contained in a second set of strings of memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Ramin Ghodsi
  • Publication number: 20210166761
    Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.
    Type: Application
    Filed: October 8, 2020
    Publication date: June 3, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: FENG PAN, JAEKWAN PARK, RAMIN GHODSI
  • Publication number: 20210065807
    Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 4, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Qiang Tang, Ramin Ghodsi
  • Publication number: 20210065825
    Abstract: Memory might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to increase a voltage level applied to each of the access lines, determine a particular voltage level at which each memory cell of a first set of strings of memory cells is deemed to be activated while increasing the voltage level applied to the access lines, decrease the voltage level applied to a particular access line without decreasing the voltage level applied to each remaining access line, and, for each memory cell connected to the particular access line and contained in a second set of strings of memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.
    Type: Application
    Filed: November 11, 2020
    Publication date: March 4, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tommaso Vali, Ramin Ghodsi
  • Patent number: 10854295
    Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Ramin Ghodsi
  • Patent number: 10854303
    Abstract: Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Ramin Ghodsi
  • Patent number: 10854301
    Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Feng Pan, Ramin Ghodsi, Qiang Tang
  • Publication number: 20200335171
    Abstract: Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
  • Patent number: 10803945
    Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Feng Pan, Jaekwan Park, Ramin Ghodsi
  • Publication number: 20200321065
    Abstract: Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tommaso Vali, Ramin Ghodsi
  • Patent number: 10714191
    Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
  • Patent number: 10714196
    Abstract: Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Ramin Ghodsi
  • Publication number: 20200111534
    Abstract: Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tommaso Vali, Ramin Ghodsi
  • Publication number: 20200089423
    Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Inventor: Ramin Ghodsi
  • Patent number: 10515692
    Abstract: Methods of operating a memory device applying a programming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a particular memory cell of the plurality of memory cells for programming while the programming pulse has a particular voltage level of the plurality of different voltage levels, and, after enabling the particular memory cell for programming, inhibiting the particular memory cell from programming while the programming pulse has a second voltage level of the plurality of different voltage levels, different than the particular voltage level.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Xiaojiang Guo, Ramin Ghodsi
  • Patent number: 10504599
    Abstract: Programming methods include programming first and second data in first and second memory cells, reading the first data from the first memory cell by applying a read voltage to an access line connected to the first and second memory cells while the first memory cell is electrically connected to a data line and while the second memory cell is electrically disconnected from the data line, reading the second data from the second memory cell by electrically disconnecting the first memory cell from the data line and electrically connecting the second memory cell to the data line while the read voltage remains applied to the access line, and programming the read first data and the read second data in a single memory cell connected to a different access line.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Ramin Ghodsi, Toru Tanzawa
  • Patent number: 10490279
    Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Ramin Ghodsi