Patents by Inventor Ramin Ghodsi
Ramin Ghodsi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10854295Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.Type: GrantFiled: November 2, 2018Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Qiang Tang, Ramin Ghodsi
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Publication number: 20200335171Abstract: Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.Type: ApplicationFiled: June 30, 2020Publication date: October 22, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
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Patent number: 10803945Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.Type: GrantFiled: June 28, 2019Date of Patent: October 13, 2020Assignee: Micron Technology, Inc.Inventors: Feng Pan, Jaekwan Park, Ramin Ghodsi
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Publication number: 20200321065Abstract: Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Ramin Ghodsi
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Patent number: 10714191Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.Type: GrantFiled: May 13, 2019Date of Patent: July 14, 2020Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
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Patent number: 10714196Abstract: Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line.Type: GrantFiled: October 5, 2018Date of Patent: July 14, 2020Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Ramin Ghodsi
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Publication number: 20200111534Abstract: Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line.Type: ApplicationFiled: October 5, 2018Publication date: April 9, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Ramin Ghodsi
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Publication number: 20200089423Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.Type: ApplicationFiled: November 22, 2019Publication date: March 19, 2020Inventor: Ramin Ghodsi
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Patent number: 10515692Abstract: Methods of operating a memory device applying a programming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a particular memory cell of the plurality of memory cells for programming while the programming pulse has a particular voltage level of the plurality of different voltage levels, and, after enabling the particular memory cell for programming, inhibiting the particular memory cell from programming while the programming pulse has a second voltage level of the plurality of different voltage levels, different than the particular voltage level.Type: GrantFiled: June 29, 2018Date of Patent: December 24, 2019Assignee: Micron Technology, Inc.Inventors: Qiang Tang, Xiaojiang Guo, Ramin Ghodsi
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Patent number: 10504599Abstract: Programming methods include programming first and second data in first and second memory cells, reading the first data from the first memory cell by applying a read voltage to an access line connected to the first and second memory cells while the first memory cell is electrically connected to a data line and while the second memory cell is electrically disconnected from the data line, reading the second data from the second memory cell by electrically disconnecting the first memory cell from the data line and electrically connecting the second memory cell to the data line while the read voltage remains applied to the access line, and programming the read first data and the read second data in a single memory cell connected to a different access line.Type: GrantFiled: October 1, 2018Date of Patent: December 10, 2019Assignee: Micron Technology, Inc.Inventors: Qiang Tang, Ramin Ghodsi, Toru Tanzawa
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Patent number: 10489079Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.Type: GrantFiled: May 31, 2017Date of Patent: November 26, 2019Assignee: Micron Technology, Inc.Inventor: Ramin Ghodsi
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Patent number: 10490279Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.Type: GrantFiled: September 6, 2018Date of Patent: November 26, 2019Assignee: Micron Technology, Inc.Inventor: Ramin Ghodsi
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Publication number: 20190325965Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: FENG PAN, JAEKWAN PARK, RAMIN GHODSI
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Publication number: 20190267102Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
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Patent number: 10388384Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.Type: GrantFiled: July 24, 2018Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
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Patent number: 10381080Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.Type: GrantFiled: September 29, 2016Date of Patent: August 13, 2019Assignee: Micron Technology, Inc.Inventors: Feng Pan, Jaekwan Park, Ramin Ghodsi
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Publication number: 20190214089Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.Type: ApplicationFiled: November 2, 2018Publication date: July 11, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Qiang Tang, Ramin Ghodsi
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Publication number: 20190214086Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.Type: ApplicationFiled: January 8, 2018Publication date: July 11, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Qiang Tang, Ramin Ghodsi
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Patent number: 10325659Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.Type: GrantFiled: January 8, 2018Date of Patent: June 18, 2019Assignee: Micron Technology, Inc.Inventors: Qiang Tang, Ramin Ghodsi
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Publication number: 20190074070Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.Type: ApplicationFiled: November 6, 2018Publication date: March 7, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Feng Pan, Ramin Ghodsi, Qiang Tang