Abstract: An embodiment of a method of programing might include applying a first voltage difference across a first memory cell to be programed, where applying the first voltage difference comprises applying a first channel bias voltage to a channel of the first memory cell, and applying a second voltage difference, substantially equal to the first voltage difference, across a second memory cell to be programed while applying the first voltage difference across the first memory-cell, where applying the second voltage difference comprises applying a second channel bias voltage to a channel of the second memory cell. The first channel bias voltage is different than the second channel bias voltage, and the first memory cell and the second memory cell are commonly coupled to an access line and are at different locations along a length of the access line.

Abstract: An embodiment of a method of programming might include applying a first voltage difference across a first memory cell to be programmed, where applying the first voltage difference comprises applying a first channel bias voltage to a channel of the first memory cell, and applying a second voltage difference, substantially equal to the first voltage difference, across a second memory cell to be programmed while applying the first voltage difference across the first memory cell, where applying the second voltage difference comprises applying a second channel bias voltage to a channel of the second memory cell. The first channel bias voltage is different than the second channel bias voltage, and the first memory cell and the second memory cell are commonly coupled to an access line and are at different locations along a length of the access line.

Abstract: The present invention discloses a level-shifting circuit to provide an initial stage to a differential amplifier circuit, a differential amplifier circuit, and a method of operating same. An example level-shifting circuit includes a first transistor and a second transistor to receive a first differential amplifier input. The first transistor has a drain receiving a power input, and the second transistor has a drain coupled to a source of the first transistor and a source coupled to a biased tail circuit. The example level-shifting circuit further includes a third transistor and a fourth transistor to receive a second differential amplifier input. The third transistor has a drain receiving a power input and the fourth transistor has a drain coupled to a source of the third transistor and a source coupled to the biased tail circuit. Other examples, methods, and apparatuses are described herein.

Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus ma include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memos subblocks.

Abstract: Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.

Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.

Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.

Abstract: Apparatuses and methods for providing power responsive a power loss are disclosed herein. A power chip may comprise a power sensor, a write command control logic, and an array. The power sensor may be configured to detect a power loss of a power supply and provide a power loss control signal responsive, at least in part, to detecting the power loss of the power supply. The write command control logic may be coupled to the power sensor and may be configured to receive the power loss control signal. The write command control logic may be further configured to provide a write command responsive, at least in part, to receipt of the power loss control signal. The array may include a plurality of capacitors configured to store power and further configured to provide power during the power loss.

Abstract: Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. A first portion of each programming pulse is used to program certain cells towards a target data state associated with a first threshold voltage level, and a later portion of each programming pulse is used to program other cells towards a target data state associated with a second threshold voltage level that is lower than the first threshold voltage level.

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract: A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described.

Abstract: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.

Abstract: Apparatuses and methods for providing power responsive a power loss are disclosed herein. A power chip may comprise a power sensor, a write command control logic, and an array. The power sensor may be configured to detect a power loss of a power supply and provide a power loss control signal responsive, at least in part, to detecting the power loss of the power supply. The write command control logic may be coupled to the power sensor and may be configured to receive the power loss control signal. The write command control logic may be further configured to provide a write command responsive, at least in part, to receipt of the power loss control signal. The array may include a plurality of capacitors configured to store power and further configured to provide power during the power loss.