Abstract: A computer-implemented method for manufacturing an integrated circuit (IC) chip includes defining digital block specifications for the IC; and automatically synthesizing and integrating digital blocks with support circuits in accordance with the digital block specifications.

Abstract: A computer-implemented method for manufacturing an integrated circuit chip includes generating a timing model for a first circuit description of an analog parallel multi-state driver circuit. The first circuit description of the analog parallel multi-state driver circuit having programmable driver states. The timing model is dependent on the driver states. The first circuit description of the analog parallel multi-state driver circuit and the generated timing model are provided for insertion into a second circuit description representing a digital system.

Abstract: Rejecting radio frequency (RF) interference in a communication system. In one aspect, rejecting RF interference includes receiving a signal on a signal path of a receiver from a communication channel, the signal including one or more received signal components having a frequency within a predetermined subset range of frequencies within an operating signal bandwidth of the receiver. The received signal components are attenuated using a notch filter to reduce RF interference obtained during transmission of the signal over the communication channel. In some embodiments, the one or more signal components have been boosted in power at a link partner transmitter connected to the communication channel.

Abstract: Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.

Abstract: Methods and apparatus for transferring data along a link with a 10GBASE-T transceiver at a variable data rate are disclosed. One exemplary method includes detecting a link quality metric; and selecting a symbol transmission rate and a data modulation scheme based on the detected link quality metric. In many implementations, for a selected symbol transmission rate, if the detected link quality metric is less than a link quality threshold, then the selecting of the data modulation scheme is performed such that a data bit per symbol value represented by the selected data modulation scheme is decreased by at least ½ data bit per symbol. The selected symbol transmission rate and the selected modulation together represent a selectable data rate from a selection of data rates.

Abstract: Methods and apparatus for transferring data along a link with a 10 GBASE-T transceiver at a variable data rate are disclosed. One exemplary method includes detecting a link quality metric; and selecting a symbol transmission rate and a data modulation scheme based on the detected link quality metric. In many implementations, for a selected symbol transmission rate, if the detected link quality metric is less than a link quality threshold, then the selecting of the data modulation scheme is performed such that a data bit per symbol value represented by the selected data modulation scheme is decreased by at least ½ data bit per symbol. The selected symbol transmission rate and the selected modulation together represent a selectable data rate from a selection of data rates.

Abstract: Methods and apparatus for transferring data along a link with a 10GBASE-T transceiver at a variable data rate are disclosed. One exemplary method includes detecting a link quality metric; and selecting a symbol transmission rate and a data modulation scheme based on the detected link quality metric. In many implementations, for a selected symbol transmission rate, if the detected link quality metric is less than a link quality threshold, then the selecting of the data modulation scheme is performed such that a data bit per symbol value represented by the selected data modulation scheme is decreased by at least ½ data bit per symbol. The selected symbol transmission rate and the selected modulation together represent a selectable data rate from a selection of data rates.

Abstract: A method is disclosed for correcting bit errors in a block-coded data frame. The method includes receiving a plurality of block-coded symbols, each symbol including at least one unencoded bit; detecting a bit error in one of the plurality of symbols associated with the unencoded bits, the detecting carried out in accordance with an error detection algorithm; identifying the symbol having the bit error from among the plurality of symbols based on the error detection algorithm; and correcting the bit error in the identified symbol.

Abstract: A circuit for a wireline system is disclosed. In an embodiment, the circuit includes a twisted pair channel. The twisted pair channel delivers a differential signal that includes a converter mode component. The circuit includes at least one transformer coupled to the twisted pair channel and a transceiver coupled to the at least one transformer. The circuit further includes a common mode detection coupled to the transceiver for detecting a common mode component. In an embodiment, the circuit detects the common mode component. Accordingly, with common mode component detection capability, the common mode component of the differential can be analyzed for characterization purposes as well as for potential improvement in the system performance signal.

Abstract: Rejecting radio frequency (RF) interference in a communication system. In one aspect, rejecting RF interference includes receiving a signal on a signal path of a receiver from a communication channel, the signal including one or more received signal components having a frequency within a predetermined subset range of frequencies within an operating signal bandwidth of the receiver. The received signal components are attenuated using a notch filter to reduce RF interference obtained during transmission of the signal over the communication channel. In some embodiments, the one or more signal components have been boosted in power at a link partner transmitter connected to the communication channel.

Abstract: Fast retraining of communication parameters for a transceiver in a communication network. In one aspect, it is determined that the transceiver has lost the communication link for data communication, and the transceiver receives a signal providing a fast retraining sequence that updates transceiver parameters in order to reacquire the link for the data communication. The fast retraining sequence is performed in a reduced time relative to a full training sequence used for initializing the parameters for data communication by the transceiver.

Abstract: A magnetic package for a communication system is disclosed the package comprises a plurality of transformers, wherein each transformer comprises a differential transformer. Each differential transformer comprises at least 2 sets of three pins. Each transformer is coupled to a twisted pair channel and a transceiver. The magnetic package includes at least one common mode transformer coupled to at least one of the transformers, wherein the at least one common mode transformer includes at least three pins. The at least three pins for the at least one common mode transformer are in a position relative to the other pins such that the package size is minimized.

Abstract: An iterative decoder configured to implement a min-sum with correction algorithm. The iterative decoder includes N parity check nodes coupled to M equality constraint nodes. The iterative decoder further includes a first parity check node configured to send an output to a first equality constraint node. Responsive to a minimum magnitude of other M?1 inputs to the first parity check node being lower than a pre-determined threshold, the parity check node sends the output having a same magnitude as that of the minimum magnitude of the other M?1 inputs to the first parity check node. Responsive to the minimum magnitude of the other M?1 inputs to the first parity check node being greater than the pre-determined threshold, the parity check node subtracts a correction factor in the form of p·2q from the minimum magnitude.

Abstract: In one implementation, a decoding architecture is provided that includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder coupled to the input buffer. The decoder is configured to receive a first codeword and a second codeword from the input buffer, and simultaneously process the first codeword and the second codeword such that each of the first codeword and the second codeword is processed only for a minimum amount of time for the first codeword or the second codeword to become decoded. The input buffer is further configured to load a third codeword into the decoder responsive to the first codeword or the second codeword being decoded.

Abstract: Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a detector including an input to receive a decoded codeword and including circuitry to detect the presence of one or more trapping sets of bits in the decoded codeword. A selection processor is coupled to the detector to select one from a group of trapping sets and correct one or more bits in the decoded codeword based on statistical measures associated with the one or more trapping sets of bits.

Abstract: Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a decoder that performs decoding operations on an encoded codeword in received data, and a detector coupled to the decoder for detecting the presence of any one of a group of possible trapping sets in the decoding operations on the encoded codeword. A selection processor is also included, coupled to the decoder, for providing a decoded codeword by selecting one trapping set of the group of possible trapping sets, the selected trapping set being present in the decoding operations of the codeword, and by using the selected trapping set to produce the decoded codeword.

Abstract: An iterative error correcting decoder is provided. In one implementation, the iterative error correcting decoder includes an equality constraint node and a parity check node, the parity check node. The parity check node includes parity logic configured to receive input data bits from the equality constraint node and determine a first minimum value and a second minimum value associated with the input data bits using a MinSum algorithm. An enhancement function is performed on the first minimum value and the second minimum value. The enhancement function compares each of the first minimum value and the second minimum value with a first pre-determined constant value, and responsive to the first minimum value and the second minimum value being smaller than the first pre-determined constant value, the enhancement function passes the first minimum value and the second minimum value without any changes as output of the MinSum algorithm.

Abstract: A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associated with a programmable transmitter that is in communication with the device. The biased bits correspond to the variable nodes of the dominant trapping set. The method further includes transmitting random data from the programmable transmitter to the device, in which the random data includes one or more of the biased bits; measuring a number of error events corresponding to biased bits received by the device that cannot be decoded; and determining a true bit error rate of the device based on the measured number of error events.

Abstract: A signal processing system includes an AGC and pre-echo cancellation system for receiving an analog signal, amplifying signal magnitude (over all frequencies) to a pre-determined level by AGC, and removing the immediate transmit pulse from this received signal by pre-echo canceller to provide a second analog signal. The signal processing system also includes a summer for receiving the analog signal; a feed forward equalization (FFE) unit for receiving a signal from the summer; and a slicer for receiving a signal from the FFE unit and providing an output signal. The signal processing system also includes an Echo and NEXT or FEXT cancellation system for receiving the output signal and for providing a signal to the summer for canceling the echo and crosstalk in the signal processing system. The Echo and crosstalk components associated with a signal processing system can be subtracted prior to the FFE.

Abstract: A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receive a first codeword from the input buffer and process the first codeword. The iterative decoder processes the first codeword only for an amount of time required for the first codeword to become substantially error free. The decoder architecture further includes logic coupled to each of the iterative decoder and the input buffer. The logic is configured to determine when the first codeword processed by the decoder becomes substantially error free. The logic further generates a signal for loading a second codeword from the input buffer into the iterative decoder responsive to the logic determining when the first codeword becomes substantially error free.