Abstract: Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a decoder that performs decoding operations on an encoded codeword in received data, and a detector coupled to the decoder for detecting the presence of any one of a group of possible trapping sets in the decoding operations on the encoded codeword. A selection processor is also included, coupled to the decoder, for providing a decoded codeword by selecting one trapping set of the group of possible trapping sets, the selected trapping set being present in the decoding operations of the codeword, and by using the selected trapping set to produce the decoded codeword.

Abstract: The line driver circuit is provided that includes a first pull-up variable resistor connected between a first power supply and the first output terminal, a second pull-up variable resistor connected between the first power supply and the second output terminal, a first pull-down variable resistor connected between a second power supply and the first output terminal, a second pull-down variable resistor connected between the second power supply and the second output terminal, a floating variable resistor connected between the first output terminal and the second output terminal, and coder logic to adjust an output voltage across the first output terminal and the second output terminal by varying a resistance of one or more of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor in response to received data bits.

Abstract: A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors for transmitting digital data over controlled-impedance transmission lines.

Abstract: A system and method for equalizing a signal is provided. In one implementation, the method includes generating a partially equalized signal from an input signal based on a plurality of coefficients associated with a feed-forward equalizer (FFE); generating decoded bit values based on the partially equalized signal, the decoded bit values being an equalized output signal; measuring error in the partially equalized signal; and adjusting the coefficients associated with the feed-forward equalizer (FFE) based on the error measured in the partially equalized signal. Values of the coefficient are not used to adjust of the coefficients associated with the feed-forward equalizer (FFE).

Abstract: A decision feedback equalizer finite impulse response (DFE FIR) filter for cancelling inter-symbol interference within a signal transmitted through a communication channel. The DFE FIR filter includes a feed-forward equalization path to receive the signal transmitted through the communication channel and generate a first partially equalized signal from the signal based on a plurality of coefficients associated with the feed-forward equalization path; a feedback equalization path to generate a second partially equalized signal that corrects for the inter-symbol interference within the signal based on an output of the DFE FIR filter; a summer to combine the first partially equalized signal with the second partially equalized signal; and a signal amplifier to receive the combined signal from the summer and generate the output of the DFE FIR filter.

Abstract: A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors is disclosed for transmitting digital data over controlled-impedance transmission lines. This invention discloses the design of a multi-level PAM driver for high-speed wireline communication, with up to four times improvement in power efficiency over conventional drivers. Two key requirements for high-speed line drivers are first generating the target voltage level onto the controlled-impedance line, and second being impedance matched to the line itself to eliminate signal reflections from the transmitter back to the line. The driver in accordance with the present invention satisfies both of these requirements at very high power efficiency.

Abstract: A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receive a first codeword from the input buffer and process the first codeword. The iterative decoder processes the first codeword only for an amount of time required for the first codeword to become substantially error free. The decoder architecture further includes logic coupled to each of the iterative decoder and the input buffer. The logic is configured to determine when the first codeword processed by the decoder becomes substantially error free. The logic further generates a signal for loading a second codeword from the input buffer into the iterative decoder responsive to the logic determining when the first codeword becomes substantially error free.

Abstract: A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors is disclosed for transmitting digital data over controlled-impedance transmission lines. The driver comprises two push-pull variable resistor branches, and a middle variable resistor branch. The purpose of the two push-pull branches is to generate the target voltage level onto the line, and the middle branch ensures that at all times the effective parallel impedance of the resistors matches to the line impedance. The values of the variable resistors are selected by a decision combinational logic whose input is the raw data bits. The driver requires a supply voltage that is equal or higher than twice the maximum output signal level. This supply voltage can be the supply voltage supplied to the chip itself or a regulated supply voltage adjusted to result in a certain voltage swing.

Abstract: A delay compensation technique for two lines or more using multiple sample/hold stages clocked by a multi-phase clock is disclosed. Each line has a delay compensation circuit so as to adjusts the delay of the line to match others. Each phase of the clock samples the input data at certain time intervals, T, where the sampling time intervals are typically equal to a symbol period. By selecting and multiplexing the proper sample/hold data to output in each delay compensation circuit, the outcoming samples are aligned within a time interval. The select signal of each multiplexer selects only one sample/hold output and rotate at a frequency of 1/T. The sample/hold stages not selected at the time can be turned off to save power. The outputs from the multiplexers of the multiple lines can be further fine aligned by continuously moving the multiplexer select signal versus the sampling clocks.

Abstract: A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors is disclosed for transmitting digital data over controlled-impedance transmission lines. The driver comprises two push-pull variable resisor branches, and a middle variable resistor branch. The purpose of the two push-pull branches is to generate the target voltage level onto the line, and the middle branch ensures that at all times the effective parallel impedance of the resistors matches to the line impedance. The values of the variable resistors are selected by a decision combinational logic whose input is the raw data bits. The driver requires a supply voltage that is equal or higher than twice the maximum output signal level. This supply votage can be the supply voltage supplied to the chip itself or a regulated supply voltage adjusted to result in a certain voltage swing.

Abstract: A signal processing system is disclosed. The signal processing system comprises an AGC and pre-echo cancellation system for receiving an analog signal, boosting it up (over all frequencies) to a pre-determined range by AGC, and removing the immediate transmit pulse from this received signal by pre-echo canceller to provide a second analog signal. The signal processing system further comprises a summer for receiving the analog signal; a feed forward equalization (FFE) unit for receiving a signal from the summer; and a slicer for receiving a signal from the FFE unit and providing an output signal. The signal processing system also comprises an Echo and NEXT cancellation system for receiving the output signal and for providing a signal to the summer for canceling the echo and crosstalk in the signal processing system. Accordingly, in a system and method in accordance with the present invention the Echo and crosstalk components associated with a signal processing system can be subtracted prior to the FFE.

Abstract: A finite impulse response (FIR) filter is disclosed. The finite impulse response (FIR) filter comprises a passive delay line and a plurality of delay stages coupled to the passive delay line. The plurality of delay stages comprises a multiplier stage. The finite impulse response (FIR) filter includes an amplifier coupled to the delay line. A finite impulse response (FIR) filter in accordance with the present invention compensates the low-pass and/or dispersive characteristics of a communication channel (cable, fiber, etc.) in a multi-Gaps link. The receiver uses the filter to cancel the inter-symbol interference (ISI) caused by the channel on the received data. In a second aspect, a decision feedback equalizer (DFE) is a non-linear filter that can cancel the non-linear dispersion effects of a channel, and therefore extends its application to a very wide range of communication channels, including but not limited to channels with linear multi-path and/or nonlinear distortion.

Abstract: A method and system for adaptive equalization without having to have a phase locked loop to recover the data bits is disclosed. This provides a clock-less equalization method. The algorithm also does not necessitate the digitization of all tap values, as is typically the case for DSP based equalizers. A system and method in accordance with the present invention can be utilized advantageously in devices where binary data is traveling through fiber (both single mode and multi-mode fiber) contaminated by certain characteristics of the fiber, which cause impairments. For a given data frequency, this impairments limit the length of the fiber that can be used for transmission of the data, and thus require equalization.

Abstract: A circuit and method for equalization of a communication signal received over a communication system transmission line using switched filter characteristics. Equalization for frequency-independent and frequency-dependent attenuation of the communication signal is accomplished with a linear equalization channel which includes an input biasing circuit which provides a common input signal to two parallel amplifier paths. One path includes a wideband, fixed-gain, frequency-independent amplifier stage. The other path is a wideband multiplier amplifier stage in series with a wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic. The outputs of the fixed-gain wideband frequency-independent amplifier stage and wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic are both tied in common to the input of a wideband gain buffer amplifier stage, which has a switchable high-frequency boost frequency response characteristic.

Abstract: A voltage-to current (V-to-I) converter circuit for use in combination with a current-controlled oscillator (ICO) to form a voltage-controlled oscillator (VCO), wherein the V-to-I converter circuit provides a current to the ICO while this current ranges itself corresponding to the process, supply voltage, and temperature needs of the ICO, thus allowing a more stabilized ICO and VCO. In one embodiment, the V-to-I circuit allows for independent adjustability to compensate for each quantity of required process, supply voltage, and temperature. In another embodiment, the V-to-I circuit includes compensation circuitry for process and temperature only. There is no need for supply voltage compensation because the supply voltage for the V-to-I converter circuit is provided from a supply that has been linearly regulated and preferably built-in on the chip.

Abstract: An improved adaptive equalizer providing the proper amount of equalization to restore the missing frequency components of a received and underequalized waveform. The invention'equalization gain or pulse counting feature can be set at various levels by digitally programming the control logic of the invention. Additionally, the digital control features of the invention permit higher accuracy in determining required equalizations for waveforms and avoid variations, such as temperature process variations, present in analog systems. The invention permits higher accuracy in determining required equalizations for waveforms. The invention finds, holds, and updates the average low frequency peak of the incoming signal in a highly digital manner. Since peak information is digitally held, it is not subject to the data dependent drifts inherent in analog peak detectors.

Abstract: A current-controlled oscillator (ICO) circuit including an all p-channel transistor based ring oscillator, a first current mirroring stage, and a second current mirroring stage. The all p-channel transistor based ring oscillator, p-channel transistors in the input structure of each amplification stage, and metal lines in the ring and from the ring to the amplification stages over an n-well improve noise immunity and tolerance. The first current mirroring stage utilizes an input current to generate a first voltage controlling a series of differential delay cells connected in a ring topology that forms the ring oscillator. The second mirroring stage utilizes a precision current to generate a second voltage controlling at least one amplification stage, which converts corresponding delay cell output signals to a single-ended logic level signal compatible with external circuitry needs.

Abstract: An improved invention providing a solution to a problem endemic to conventional adaptive equalizer systems, a problem known as baseline wander. The invention brings the baseline back down when it has drifted up due to baseline wander. The invention brings the baseline back up when it has drifted down due to baseline wander. The end result is that the invention keeps the data centered about the common mode, thus helping to ensure that the data is equalized properly without distortion.

Abstract: Support for a mixed network environment is provided which can contain multiple isochronous and/or non-isochronous LAN protocols such as Isochronous-Ethernet, Ethernet, isochronous-token ring, token ring, other isochronous-LAN or other LAN Systems. Support for a mixed environment includes a protocol detection mechanism which is embodied in a handshaking scheme. This handshaking scheme determines the signalling capability at the end points of the link and implements the correct protocol. This enables isochronous nodes and hubs to automatically detect the presence of Ethernet, token ring, or other LAN equipment at the other and of the network cable. If this detection occurs, the isochronous LAN equipment will fall-back to a LAN compliant mode of operation. Typically, only the hub will have the capability of operating in different networking modes, such as Ethernet, Token Ring isochronous modes.

Abstract: Support for a mixed network environment is provided which can contain multiple isochronous and/or non-isochronous LAN protocols such as Isochronous-Ethernet. Ethernet, isochronous-token ring, token ring, other isochronous-LAN or other LAN Systems. Support for a mixed environment includes a protocol detection mechanism which is embodied in a handshaking scheme. This handshaking scheme determines the signalling capability at the end points of the link and implements the correct protocol. This enables isochronous nodes and hubs to automatically detect the presence of Ethernet, token ring, or other LAN equipment at the other and of the network cable. If this detection occurs, the isochronous LAN equipment will fall-back to a LAN compliant mode of operation. Typically, only the hub will have the capability of operating at different networking modes, such as Ethernet, Token Ring isochronous modes.