Patents by Inventor Raminda U. Madurawe
Raminda U. Madurawe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6108239Abstract: A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory cell. Data may be stored the memory cell of the present invention for the required lifetime of the memory cell usage, and data is retained even when power is removed. The memory cell of the present invention has a substantially transverse or vertical channel (140), relative to a surface of a substrate. The memory may be used to create very high-density memory arrays.Type: GrantFiled: May 26, 1999Date of Patent: August 22, 2000Assignee: Altera CorporationInventors: Seshan Sekariapuram, Raminda U. Madurawe
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Patent number: 6091102Abstract: A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory cell. Data may be stored the memory cell of the present invention for the required lifetime of the memory cell usage, and data is retained even when power is removed. The memory cell of the present invention has a substantially transverse or vertical channel (140), relative to a surface of a substrate. The memory may be used to create very high-density memory arrays.Type: GrantFiled: March 13, 1998Date of Patent: July 18, 2000Assignee: Altera CorporationInventors: Seshan Sekariapuram, Raminda U. Madurawe
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Patent number: 6081449Abstract: A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory cell. Data may be stored the memory cell of the present invention for the required lifetime of the memory cell usage, and data is retained even when power is removed. The memory cell of the present invention has a substantially transverse or vertical channel (140), relative to a surface of a substrate. The memory may be used to create very high-density memory arrays.Type: GrantFiled: May 26, 1999Date of Patent: June 27, 2000Assignee: Altera CorporationInventors: Seshan Sekariapuram, Raminda U. Madurawe
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Patent number: 6078521Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 30, 1999Date of Patent: June 20, 2000Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6052309Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 30, 1999Date of Patent: April 18, 2000Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6028787Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, the logic output from this memory cell (400) is at about voltage level at a first conductor (505); and in a second state, the logic output is at about a voltage level at a second conductor (510). The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between the first conductor (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and the second conductor (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed.Type: GrantFiled: May 27, 1998Date of Patent: February 22, 2000Assignee: Altera CorporationInventors: James D. Sansbury, Raminda U. Madurawe
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Patent number: 6018476Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store she configuration information for a programmable logic device (121).Type: GrantFiled: November 18, 1997Date of Patent: January 25, 2000Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6005806Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: September 16, 1996Date of Patent: December 21, 1999Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6002182Abstract: A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.Type: GrantFiled: March 13, 1998Date of Patent: December 14, 1999Assignee: Altera CorporationInventor: Raminda U. Madurawe
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Patent number: 5998295Abstract: A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.Type: GrantFiled: December 23, 1996Date of Patent: December 7, 1999Assignee: Altera CorporationInventor: Raminda U. Madurawe
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Patent number: 5998263Abstract: A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory cell. Data may be stored the memory cell of the present invention for the required lifetime of the memory cell usage, and data is retained even when power is removed. The memory cell of the present invention has a substantially transverse or vertical channel (140), relative to a surface of a substrate. The memory may be used to create very high-density memory arrays.Type: GrantFiled: May 12, 1997Date of Patent: December 7, 1999Assignee: Altera CorporationInventors: Seshan Sekariapuram, Raminda U. Madurawe
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Patent number: 5949710Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.Type: GrantFiled: October 30, 1996Date of Patent: September 7, 1999Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 5943267Abstract: A compact nonvolatile programmable memory cell. The memory cell has a floating gate (118), control gate (123), drain (108), and source regions (112). The memory cell is an electrically erasable programmable read only memory (EEPROM) cell or a Flash memory cell. Data may be stored the memory cell of the present invention for the required lifetime of the memory cell usage, and data is retained even when power is removed. The memory cell of the present invention has a substantially transverse or vertical channel (140), relative to a surface of a substrate. The memory may be used to create very high-density memory arrays.Type: GrantFiled: June 12, 1998Date of Patent: August 24, 1999Assignee: Altera CorporationInventors: Seshan Sekariapuram, Raminda U. Madurawe
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Patent number: 5905675Abstract: Disclosed is a method for biasing dual row line EEPROM cells. The new biasing scheme improves the data retention lifetime of an EEPROM cell by reducing the potential difference between the control gate and the write column of the cell, which reduces the tunnel oxide electric field. In a preferred embodiment, the method involves applying bias voltages to the control gate and write column of an EEPROM cell such that the potential difference between the control gate and the right column is no more than about 0.5 volts. By biasing the cell's write column to a positive voltage, the tunnel oxide field may be significantly reduced. Moreover, the invention provides a method of selecting a write column voltage based on a control gate voltage such that the tunnel oxide field is substantially balanced in all its modes. This biasing scheme minimizes SILC and improves cell reliability.Type: GrantFiled: December 22, 1997Date of Patent: May 18, 1999Assignee: Altera CorporationInventors: Raminda U. Madurawe, Richard G. Smolen, Minchang Liang, James D. Sansbury, John E. Turner, John C. Costello, Myron W. Wong
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Patent number: 5898630Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is dynamic, nonvolatile, and reprogrammable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a first programmable memory element (515). First programmable memory element (515) is coupled between a voltage source (510) and an output node (405). A charge pumping node (545) dynamically charges, through a charging transistor (525), the output node (405) to about VDD. When programmable memory element (515) is not programmed, the memory cell stores and outputs a logic low. When programmable memory element (515) is programmed, the memory cell stores and outputs a logic high. The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: November 3, 1997Date of Patent: April 27, 1999Assignee: Altera CorporationInventor: Raminda U. Madurawe
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Patent number: 5812450Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, the logic output from this memory cell (400) is at about voltage level at a first conductor (505); and in a second state, the logic output is at about a voltage level at a second conductor (510). The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between the first conductor (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and the second conductor (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed.Type: GrantFiled: August 22, 1996Date of Patent: September 22, 1998Assignee: Altera CorporationInventors: James D. Sansbury, Raminda U. Madurawe
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Patent number: 5805516Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is dynamic, nonvolatile, and reprogrammable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a first programmable memory element (515). First programmable memory element (515) is coupled between a voltage source (510) and an output node (405). A charge pumping node (545) dynamically charges, through a charging transistor (525), the output node (405) to about VDD. When programmable memory element (515) is not programmed, the memory cell stores and outputs a logic low. When programmable memory element (515) is programmed, the memory cell stores and outputs a logic high. The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 30, 1996Date of Patent: September 8, 1998Assignee: Altera CorporationInventor: Raminda U. Madurawe
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Patent number: 5740110Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is dynamic, nonvolatile, and reprogrammable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a first programmable memory element (515). First programmable memory element (515) is coupled between a voltage source (510) and an output node (405). A charge pumping node (545) dynamically charges, through a charging transistor (525), the output node (405) to about VDD. When programmable memory element (515) is not programmed, the memory cell stores and outputs a logic low. When programmable memory element (515) is programmed, the memory cell stores and outputs a logic high. The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 30, 1996Date of Patent: April 14, 1998Assignee: Altera CorporationInventor: Raminda U. Madurawe
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Patent number: 5729495Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is dynamic, nonvolatile, and reprogrammable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a first programmable memory element (515). First programmable memory element (515) is coupled between a voltage source (510) and an output node (405). A charge pumping node (545) dynamically charges, through a charging transistor (525), the output node (405) to about VDD. When programmable memory element (515) is not programmed, the memory cell stores and outputs a logic low. When programmable memory element (515) is programmed, the memory cell stores and outputs a logic high. The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: September 29, 1995Date of Patent: March 17, 1998Assignee: Altera CorporationInventor: Raminda U. Madurawe
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Patent number: 5581501Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, a logic high output from this memory cell (400) is at about VDD; and in a second state, a logic low output is about VSS. The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between VDD (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and VSS (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed. In the second state, first programmable memory element (515) is programmed, while second programmable memory element (520) is not programmed.Type: GrantFiled: August 17, 1995Date of Patent: December 3, 1996Assignee: Altera CorporationInventors: James D. Sansbury, Raminda U. Madurawe