Patents by Inventor Raminda Udaya Madurawe

Raminda Udaya Madurawe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programmable structured arrays
    Patent number: 10594320
    Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: March 17, 2020
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Three dimensional integrated-circuits
    Patent number: 10447272
    Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 15, 2019
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
    Publication number: 20190279993
    Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventor: Raminda Udaya Madurawe
  • Timing exact design conversions from FPGA to ASIC
    Patent number: 10339245
    Abstract: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: July 2, 2019
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Pads and pin-outs in three dimensional integrated circuits
    Patent number: 10304854
    Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: May 28, 2019
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
    Publication number: 20180277549
    Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 27, 2018
    Inventor: Raminda Udaya Madurawe
  • THREE DIMENSIONAL INTEGRATED CIRCUITS
    Publication number: 20180167071
    Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
    Type: Application
    Filed: February 9, 2018
    Publication date: June 14, 2018
    Inventor: Raminda Udaya Madurawe
  • PROGRAMMABLE STRUCTURED ARRAYS
    Publication number: 20180159537
    Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.
    Type: Application
    Filed: January 22, 2018
    Publication date: June 7, 2018
    Inventor: Raminda Udaya Madurawe
  • Pads and pin-outs in three dimensional integrated circuits
    Patent number: 9978773
    Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: May 22, 2018
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Three dimensional integrated circuits
    Patent number: 9912336
    Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: March 6, 2018
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Programmable structured arrays
    Patent number: 9882567
    Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 30, 2018
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
    Publication number: 20170278850
    Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventor: Raminda Udaya Madurawe
  • Pads and pin-outs in three dimensional integrated circuits
    Patent number: 9679914
    Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: June 13, 2017
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • TIMING EXACT DESIGN CONVERSIONS FROM FPGA TO ASIC
    Publication number: 20170124241
    Abstract: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.
    Type: Application
    Filed: January 16, 2017
    Publication date: May 4, 2017
    Inventor: Raminda Udaya MADURAWE
  • PROGRAMMABLE STRUCTURED ARRAYS
    Publication number: 20160308535
    Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 20, 2016
    Inventor: Raminda Udaya Madurawe
  • Programmable structured arrays
    Patent number: 9397665
    Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: July 19, 2016
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • THREE DIMENSIONAL INTEGRATED CIRCUITS
    Publication number: 20160134288
    Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
    Type: Application
    Filed: November 23, 2015
    Publication date: May 12, 2016
    Inventor: Raminda Udaya Madurawe
  • Three dimensional integrated circuits
    Patent number: 9240790
    Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: January 19, 2016
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
    Publication number: 20160013192
    Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
    Type: Application
    Filed: May 18, 2015
    Publication date: January 14, 2016
    Inventor: Raminda Udaya Madurawe
  • Pads and pin-outs in three dimensional integrated circuits
    Patent number: 9070668
    Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: June 30, 2015
    Inventor: Raminda Udaya Madurawe