Abstract: Time-multiplexed interconnect structures, timing optimization techniques and software tools for said structures, for programmable semiconductor ICs is disclosed. A first aspect is a programmable logic device, wherein a plurality of outputs from logic blocks is coupled to a plurality of inputs to logic blocks by a single wire segment comprising a programmable time multiplexing method. A second aspect is a software placement and route tool, wherein a plurality of routs is assigned to a single route, wherein the plurality of routs is routed in the single route by a time multiplexed method. A third aspect is a critical signal propagation path in a programmable logic device comprising global non-overlapping control signals and time multiplexed wires, wherein each control signal assigns a programmable time slot for multiple signals within one of said wires, further comprising one or more critical signals assigned to the last multiplexed time slot.

Abstract: A method of fabricating a low temperature semiconductor thin film device is described. The method includes: forming one or more metal lines on a substrate; forming a conductive contact to a said metal line; forming a thin film device having: a first amorphous silicon region, wherein a portion of the region covers a said conductive contact; and a gate dielectric layer; and a second amorphous silicon layer; forming a silicide of first and second amorphous silicon material with a deposited metallic material; depositing an insulating material; and forming conductive contacts and top metal interconnects to couple said first and second amorphous silicon regions.

Abstract: Methods of fabricating low temperature semiconductor thin film switching devices are described.

Abstract: A configurable look up table (LUT) structure of an integrated circuit comprising: a first, a second and a third intermediate LUT stage, each of the LUT stages comprising one or more inputs and an output, wherein: the output of first intermediate LUT stage is coupled to an input of the second and third intermediate LUT stages; and the second intermediate LUT stage generates an arithmetic function of two bits and a carry-in signal received as inputs to the LUT structure; and the third intermediate LUT stage generates a carry-out signal.

Abstract: A semiconductor device includes a plurality of circuit blocks; and a configuration circuit coupled to the plurality of circuit blocks to program the circuit blocks, the configuration circuit comprising a plurality of memory elements, the memory elements further comprising: a first set of memory elements to store a first instruction; and a second set of memory elements to store a second instruction; and a global control signal to select the first or second instruction in the configuration circuit to program the circuit blocks.

Abstract: A programmable integrated circuit (IC), wherein: a programmable logic circuit is programmed to a user specification by configuring a transistor gate control signal generated by a read only memory (ROM) element positioned substantially above or below the transistor.

Abstract: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

Abstract: A three-dimensional semiconductor device, comprising: a programmable logic circuit; and a configuration circuit comprising a non planar memory element, wherein: a portion of the memory element is positioned above or below the logic circuit; and an output of the memory element is coupled to the logic circuit to program the logic circuit.

Abstract: A semiconductor device includes a plurality of circuit blocks; and a configuration circuit coupled to the plurality of circuit blocks to program the circuit blocks, the configuration circuit comprising a plurality of memory elements, the memory elements further comprising: a first set of memory elements to store a first instruction; and a second set of memory elements to store a second instruction; and a global control signal to select the first or second instruction in the configuration circuit to program the circuit blocks.

Abstract: In a first aspect, a three-dimensional semiconductor device, wherein: a configurable memory element coupled to a programmable logic circuit to program the logic circuit is positioned substantially above the logic circuit. In a second aspect, a three-dimensional semiconductor device, comprising: a first module layer having a circuit block; and a second module layer positioned substantially above the first module layer, comprising a configuration circuit coupled to the circuit block to program the circuit block.

Abstract: Timing exact design conversions from an original field programmable device to an application specific device is disclosed. In a first aspect, a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC) comprises a user configurable element in the FPGA replaced by a mask configurable element in the ASIC. In a second aspect, an FPGA design conversion to an ASIC comprises converting a user configurable memory bit pattern generated by a software tool to program the programmable content of the FPGA to a hard-wired metal pattern for the ASIC.

Abstract: A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises programmable logic blocks and a configuration circuit with multiple sets of configuration memory, each set programmed to hold an optimized segment. Either random access memory (RAM) or mask configured read only memory (ROM) store the partitioned segments.

Abstract: A programmable look-up-table (LUT) structure adapted for carry logic incrementer implementation in an integrated circuit, comprising: three or more data inputs and a carry-in input, said data inputs comprised of consecutive bits in a data string, said carry-in comprised of the increment value to the least order bit of said data string; and three or more data outputs and a carry-out output, said data outputs comprised of the incremented values of said data inputs, and said carry-out resulting from the incremented value of the highest order bit of said data inputs; wherein, said three or more data outputs are computed in a single carry computation stage within the LUT structure.

Abstract: A programmable interconnect structure to couple a first wire segment to a second wire segment of an integrated circuit comprising: a pass-gate to electrically couple the first wire segment to the second wire segment fabricated on a substrate layer; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer, wherein changing data stored in the memory element provides a programmable method to achieve one of: isolate said first wire segment from sad second wire segment; and couple said first wire segment to said second wire segment.

Abstract: Programmable routing structures to couple physical memory nodes to logical memory nodes in embedded multi-port memory FPGA's are disclosed. In a first embodiment, a plurality of physical domain nodes couples a plurality of variable node sets in a logical read domain, wherein a configuration element activates one of the sets and selects a fixed input or an address signal to decode the data read. In a second embodiment, a plurality of physical domain nodes couples a plurality of variable node sets in a logical write domain, wherein a configuration element activates one of the sets and couples a fixed input or an address signal to an enable signal of a driver device to decode the data written. A third embodiment provide logical read and logical write functions for a single port in a multi-port physical memory array, wherein the logical read data width and the logical write data width can be independently configured, and wherein the read and write functions share common address lines.

Abstract: A programmable semiconductor device, wherein: a user programmable switch comprising a configurable element is positioned above a transistor gate material layer deposited on a silicon substrate layer.

Abstract: A method of fabricating a field programmable integrated circuit comprised of: constructing a semiconductor device comprising a fuse circuit to customize the logic content of a programmable logic circuit; and attaching said semiconductor device in a detachable lid package, wherein the fuses are customized in the field by detaching the lid and blowing one or more fuse elements. The said method further comprised of: providing a custom hard-wire pattern in lieu of the fuse circuit, wherein the programmable logic circuit timing is identical between the fuse circuit and hard-wire options.

Abstract: An inexpensive, re-configurable storage circuit for programmable logic devices and application specific integrated circuits is disclosed. The storage circuit comprises: at least one output; and at least two inputs; and at least a one input and a two input response sequence, wherein the inputs change the output in a well defined response sequence; and a configuration circuit comprising one or more memory elements, wherein the memory bits are programmed to select one of said response sequences.

Abstract: A look up table (LUT) structure, comprising: a first intermediate LUT stage comprising a LUT value input and an output; and a configurable multiplexer (MUX) comprising: an input coupled to a carry in logic signal; and an output coupled to said LUT value input of first intermediate LUT stage; wherein, said first intermediate LUT stage output generates a carry out logic signal.

Abstract: A configuration circuit, comprising: a configurable storage element coupled between a ground voltage and a first voltage, said storage element generating an output; and a voltage conversion circuit coupled between the ground voltage and a second voltage at a lower level than said first voltage, said circuit further coupled to said output; wherein, the voltage conversion circuit generates a configurable control signal either at the ground voltage level or the second voltage level by configuring the storage element.