Patents by Inventor Ranbir Singh

Ranbir Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250130543
    Abstract: A method for determining system excitation by at least one input signal for model-based control of a technical system includes (i) providing the at least one input signal, wherein the at least one input signal physically affects at least one parameter of the technical system, (ii) defining at least one distribution assumption for the at least one parameter, (iii) defining a target function for optimizing the at least one input signal taking into account the at least one defined distribution assumption, the target function optimizing the at least one input signal at least based on a weighting of a sensitivity of the input signal, (iv) determining a numerical algorithm for solving the defined target function and an uncertainty quantification method for determining the sensitivity of the at least one input signal, (v) optimizing the defined target function based on the determined numerical algorithm and the determined uncertainty quantification method, and (vi) determining the system excitation based on the opti
    Type: Application
    Filed: October 12, 2024
    Publication date: April 24, 2025
    Inventors: Kevin Schmidt, Nicola Henkelmann, Ranbir Singh, Stefan Gruener
  • Patent number: 12266691
    Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 1, 2025
    Assignee: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 12199149
    Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: January 14, 2025
    Assignee: GENESIC SEMICONDUCTOR INC.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 12051720
    Abstract: An embodiment relates to a device comprising a first section and a second section. The first section comprises a first metal oxide semiconductor (MOS) interface comprising a first portion and a second portion. The first portion comprises a first contact with a horizontal surface of a semiconductor substrate and the second portion comprises a second contact with a trench sidewall of a trench region of the semiconductor substrate. The second section comprises one of a second metal oxide semiconductor (MOS) interface and a metal region. The second MOS interface comprises a third contact with the trench sidewall of the trench region. The metal region comprises a fourth contact with a first conductivity type drift layer. The first section and the second section are located contiguously within the device along a lateral direction.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: July 30, 2024
    Assignee: GENESIC SEMICONDUCTOR INC.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Publication number: 20240222505
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device is described herein. The MOSFET device comprises a unit cell on a silicon carbide (SiC) substrate. The unit cell comprises: a source region; a well region; and a source attachment region. The source attachment region is in contact with the source region. The source attachment region is doped using first conductivity type ions. In an embodiment, the source attachment region is doped using second conductivity type ions. The source attachment region comprises a depth shallower than a depth of source region. In an embodiment, the source attachment region comprises a depth equal to a depth of the source region. The source attachment region comprises a doping concentration lower than a doping concentration of the source region. In an embodiment, the source attachment region comprises a doping concentration equal to a doping concentration of the source region.
    Type: Application
    Filed: January 15, 2024
    Publication date: July 4, 2024
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11990519
    Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: May 21, 2024
    Assignee: GENESIC SEMICONDUCTOR INC.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Publication number: 20240128348
    Abstract: An embodiment relates to a method obtaining a silicon carbide wafer comprising a first conductivity type substrate and a first conductivity type drift layer, forming a second conductivity type first well region within the first conductivity type drift layer, forming a first conductivity type source region within the second conductivity type first well region, forming a second conductivity type plug region under the first conductivity type source region, forming a gate oxide layer, forming a patterned gate metal layer, depositing an interlevel dielectric (ILD) layer, forming a first patterned mask layer on top of the ILD layer, and etching the ILD layer and the first conductivity type source region using the first patterned mask layer, and forming a silicide layer, wherein the silicide layer is in contact with a vertical sidewall of the first conductivity type source region and at-least one second conductivity type region.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11905063
    Abstract: The present invention is an apparatus and method for cutting individual label strips from a roll of label web utilizing a cutter assembly. A label cutter comprises a cutter assembly for continuously and independently controlling the rotational speeds of a rotating cutter shaft, a stationary shaft, and a label feed roller is provided. The length of the label strip is controlled by the distinct speed of rotation of a stationary knife, the stationary knife is rotatably coupled to the stationary shaft. At least one cutter blade is operatively associated to the rotating cutter shaft for cutting the label web. The stationary knife rotates with a to speed of rotation different from the speed of rotation of the cutter blade to produce longer or shorter label length strips. The frequency at which the cutter blade meets the stationary knife is inversely related to the length of the label strip that is produced during cut off.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: February 20, 2024
    Assignee: Elum Inc.
    Inventors: Ranbir Singh Claire, Vinay Leeladhar Piratla, Karmen Claire
  • Patent number: 11908933
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device is described herein. The MOSFET device comprises a unit cell on a silicon carbide (SiC) substrate. The unit cell comprises: a source region; a well region; and a source attachment region. The source attachment region is in contact with the source region. The source attachment region is doped using first conductivity type ions. In an embodiment, the source attachment region is doped using second conductivity type ions. The source attachment region comprises a depth shallower than a depth of source region. In an embodiment, the source attachment region comprises a depth equal to a depth of the source region. The source attachment region comprises a doping concentration lower than a doping concentration of the source region. In an embodiment, the source attachment region comprises a doping concentration equal to a doping concentration of the source region.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: February 20, 2024
    Assignee: GENESIC SEMICONDUCTOR INC.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11901432
    Abstract: An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N? drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: February 13, 2024
    Assignee: GENESIC SEMICONDUCTOR INC.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11862669
    Abstract: An embodiment relates to a device comprising a first section and a second section. The first section comprises a first metal oxide semiconductor (MOS) interface comprising a first portion and a second portion. The first portion comprises a first contact with a horizontal surface of a semiconductor substrate and the second portion comprises a second contact with a trench sidewall of a trench region of the semiconductor substrate. The second section comprises one of a second metal oxide semiconductor (MOS) interface and a metal region. The second MOS interface comprises a third contact with the trench sidewall of the trench region. The metal region comprises a fourth contact with a first conductivity type drift layer. The first section and the second section are located contiguously within the device along a lateral direction.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: January 2, 2024
    Assignee: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11798994
    Abstract: An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N? drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: October 24, 2023
    Assignee: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Publication number: 20230282744
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device is described herein. The MOSFET device comprises a unit cell on a silicon carbide (SiC) substrate. The unit cell comprises: a source region; a well region; and a source attachment region. The source attachment region is in contact with the source region. The source attachment region is doped using first conductivity type ions. In an embodiment, the source attachment region is doped using second conductivity type ions. The source attachment region comprises a depth shallower than a depth of source region. In an embodiment, the source attachment region comprises a depth equal to a depth of the source region. The source attachment region comprises a doping concentration lower than a doping concentration of the source region. In an embodiment, the source attachment region comprises a doping concentration equal to a doping concentration of the source region.
    Type: Application
    Filed: March 4, 2022
    Publication date: September 7, 2023
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Publication number: 20230257862
    Abstract: The present invention relates to a manufacturing method of a steel strip, a steel strip with controlled decarburized depth, a spot welded joint and the use of said steel strip or said spot welded joint. This invention is particularly well suited for the automotive industry due to the improvement of the Liquid Metal Embrittlement (LME) resistance along with target mechanical properties.
    Type: Application
    Filed: April 22, 2021
    Publication date: August 17, 2023
    Inventors: Ranbir Singh JAMWAL, Hassan GHASSEMI-ARMAKI, Anirban CHAKRABORTY, Pavan CHALLA VENKATASURYA
  • Patent number: 11682694
    Abstract: An embodiment relates to a method and manufacture of robust, high-performance devices. The method comprises preparing a unit cell of a Silicon Carbide (SiC) substrate comprising a first conductivity type substrate and a first conductivity type drift layer; forming a second conductivity type well region; forming a first conductivity type source region within the second conductivity type well region; and forming a second conductivity type shield region surrounding the first conductivity type source region. The second conductivity type shield region formed comprises a portion of the second conductivity type shield region located on a SiC surface.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: June 20, 2023
    Assignee: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11626487
    Abstract: An embodiment relates to a semiconductor component, comprising a semiconductor body of a first conductivity type comprising a voltage blocking layer and islands of a second conductivity type on a contact surface and optionally a metal layer on the voltage blocking layer, and a first conductivity type layer comprising the first conductivity type not in contact with a gate dielectric layer or a source layer that is interspersed between the islands of the second conductivity type.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 11, 2023
    Assignee: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Publication number: 20230040858
    Abstract: An embodiment relates to a device comprising a first section and a second section. The first section comprises a first metal oxide semiconductor (MOS) interface comprising a first portion and a second portion. The first portion comprises a first contact with a horizontal surface of a semiconductor substrate and the second portion comprises a second contact with a trench sidewall of a trench region of the semiconductor substrate. The second section comprises one of a second metal oxide semiconductor (MOS) interface and a metal region. The second MOS interface comprises a third contact with the trench sidewall of the trench region. The metal region comprises a fourth contact with a first conductivity type drift layer. The first section and the second section are located contiguously within the device along a lateral direction.
    Type: Application
    Filed: October 21, 2022
    Publication date: February 9, 2023
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11572214
    Abstract: The present invention is an apparatus and method for cutting individual label strips from a roll of label web utilizing a cutter assembly. A label cutter comprises a cutter assembly for continuously and independently controlling the rotational speeds of a rotating cutter shaft, a stationary shaft, and a label feed roller is provided. The length of the label strip is controlled by the distinct speed of rotation of a stationary knife, the stationary knife is rotatably coupled to the stationary shaft. At least one cutter blade is operatively associated to the rotating cutter shaft for cutting the label web. The stationary knife rotates with a speed of rotation different from the speed of rotation of the cutter blade to produce longer or shorter label length strips. The frequency at which the cutter blade meets the stationary knife is inversely related to the length of the label strip that is produced during cut off.
    Type: Grant
    Filed: August 8, 2021
    Date of Patent: February 7, 2023
    Assignee: Elum, Inc.
    Inventors: Ranbir Singh Claire, Vinay Leeladhar Piratla, Karmen Claire
  • Publication number: 20220384565
    Abstract: An embodiment relates to a method and manufacture of robust, high-performance devices. The method comprises preparing a unit cell of a Silicon Carbide (SiC) substrate comprising a first conductivity type substrate and a first conductivity type drift layer; forming a second conductivity type well region; forming a first conductivity type source region within the second conductivity type well region; and forming a second conductivity type shield region surrounding the first conductivity type source region. The second conductivity type shield region formed comprises a portion of the second conductivity type shield region located on a SiC surface.
    Type: Application
    Filed: February 22, 2022
    Publication date: December 1, 2022
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Publication number: 20220367640
    Abstract: A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (?m). A width of the unit cell is one of less than and equal to 5.0 micrometers (?.m). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.
    Type: Application
    Filed: March 4, 2022
    Publication date: November 17, 2022
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park