Patents by Inventor Ranbir Singh

Ranbir Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LIGANDS
    Publication number: 20120142918
    Abstract: A caged phosphine product is provided which can act as a ligand to form a metal complex. The metal complex can be used as a catalyst.
    Type: Application
    Filed: January 26, 2010
    Publication date: June 7, 2012
    Inventors: Ranbir Singh Padda, Martin Barry Smith, Gordon Findlay Docherty, Michael John Harrison
  • Extrusion Application System
    Publication number: 20110244115
    Abstract: A machine and a method of applying a non-Newtonian liquid composition onto a surface in a controlled manner. The composition is held in a chamber at a controlled variable pressure and is dispensed through a slit die nozzle as controlled by a valve. Characteristics of the composition are empirically developed and provided to a logic control circuit to assure that the composition is dispensed on either the entire surface or in one or more precise locations.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 6, 2011
    Applicant: B&H MANUFACTURING COMPANY, INC.
    Inventors: Svatoboj Otruba, Ranbir Singh Claire
  • Robust shallow trench isolation structures and a method for forming shallow trench isolation structures
    Patent number: 8022481
    Abstract: In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: September 20, 2011
    Assignee: Agere Systems Inc.
    Inventors: Arun K. Nanda, Nace Rossi, Ranbir Singh
  • Method to improve metal defects in semiconductor device fabrication
    Patent number: 7982286
    Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion of the thickness of the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer imparts a stress to the first portion that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the thickness of the metal layer is then deposited over the stress-compensating layer.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: July 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Nace Rossi, Ranbir Singh
  • Power switching transistors
    Patent number: 7982239
    Abstract: In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: July 19, 2011
    Assignee: Northrop Grumman Corporation
    Inventors: Ty R. McNutt, Eric J. Stewart, Rowland C. Clarke, Ranbir Singh, Stephen Van Campen, Marc E. Sherwin
  • Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow
    Patent number: 7923340
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: April 12, 2011
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Shallow trench isolation structures and a method for forming shallow trench isolation structures
    Patent number: 7906407
    Abstract: A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is etched to form a trench therein underlying the first opening. Silicon dioxide fills both the opening and the trench to form the shallow trench isolation structure, with the silicon dioxide in the opening exhibiting a negative taper angle to avoid formation of conductive stringers during subsequent process steps.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: March 15, 2011
    Assignee: Agere Systems Inc.
    Inventors: Nace Rossi, Ranbir Singh, Arun K. Nanda
  • Method to improve writer leakage in SiGe bipolar device
    Patent number: 7898038
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: March 1, 2011
    Assignee: Agere Systems, Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
  • Minimizing degradation of SiC bipolar semiconductor devices
    Patent number: 7880171
    Abstract: A bipolar device has at least one p? type layer of single crystal silicon carbide and at least one n? type layer of single crystal silicon carbide, wherein those portions of those stacking faults that grow under forward operation are segregated from at least one of the interfaces between the active region and the remainder of the device.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: February 1, 2011
    Assignee: Cree, Inc.
    Inventors: Joseph J. Sumakeris, Ranbir Singh, Michael James Paisley, Stephan Georg Mueller, Hudson M. Hobgood, Calvin H. Carter, Jr., Albert Augustus Burk, Jr.
  • Method, apparatus, material, and system of using a high gain avalanche photodetector transistor
    Patent number: 7843030
    Abstract: Here, we demonstrate new material/structures for the photodetectors, using semiconductor material. For example, we present the Tunable Avalanche Wide Base Transistor as a photodetector. Particularly, SiC, GaN, AlN, Si and Diamond materials are given as examples. The desired properties of an optimum photodetector is achieved. Different variations are discussed, both in terms of structure and material.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: November 30, 2010
    Inventor: Ranbir Singh
  • METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE
    Publication number: 20100264478
    Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
    Type: Application
    Filed: October 31, 2007
    Publication date: October 21, 2010
    Applicant: Agere Systems Inc.
    Inventors: Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Method and apparatus for hot carrier programmed one time programmable (OTP) memory
    Patent number: 7764541
    Abstract: One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: July 27, 2010
    Assignee: Agere Systems Inc.
    Inventors: Ross Alan Kohler, Richard Joseph McPartland, Ranbir Singh
  • METHOD TO REDUCE COLLECTOR RESISTANCE OF A BIPOLAR TRANSISTOR AND INTEGRATION INTO A STANDARD CMOS FLOW
    Publication number: 20100065920
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
    Type: Application
    Filed: February 14, 2007
    Publication date: March 18, 2010
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Device and method to eliminate shorting induced by via to metal misalignment
    Patent number: 7675179
    Abstract: The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: March 9, 2010
    Assignee: Agere Systems Inc.
    Inventors: Ranbir Singh, Sen Sidhartha, Nace Rossi
  • METHOD TO IMPROVE WRITER LEAKAGE IN SiGe BIPOLAR DEVICE
    Publication number: 20090236668
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
    Type: Application
    Filed: June 2, 2009
    Publication date: September 24, 2009
    Applicant: LSI Corporation
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
  • Method to improve writer leakage in a SiGe bipolar device
    Patent number: 7557010
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: July 7, 2009
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh
  • ROBUST SHALLOW TRENCH ISOLATION STRUCTURES AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES
    Publication number: 20090127651
    Abstract: In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.
    Type: Application
    Filed: January 21, 2009
    Publication date: May 21, 2009
    Inventors: Arun K. Nanda, Nace Rossi, Ranbir Singh
  • Robust shallow trench isolation structures and a method for forming shallow trench isolation structures
    Patent number: 7514336
    Abstract: In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: April 7, 2009
    Assignee: Agere Systems Inc.
    Inventors: Arun K. Nanda, Nace Rossi, Ranbir Singh
  • METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE
    Publication number: 20090050977
    Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
    Type: Application
    Filed: October 23, 2008
    Publication date: February 26, 2009
    Applicant: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Power switching transistors
    Publication number: 20080308838
    Abstract: In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode.
    Type: Application
    Filed: June 13, 2007
    Publication date: December 18, 2008
    Inventors: Ty R. McNutt, Eric J. Stewart, Rowland C. Clarke, Ranbir Singh, Stephen Van Campen, Marc E. Sherwin