Abstract: A process for manufacturing hot rolled high strength dual phase steels. In some instances, hot rolled strip is continuously cooled to less than 100° C. prior to coiling using a cooling rate between 40-70° C./second. In other instances, hot rolled strip is cooled to less than 100° C. prior to coiling using a step cooling treatment. In yet other instances, hot rolled strip is continuously cooled to less than 100° C. prior to coiling using a cooling rate between 70-100° C./second. For hot rolled strip subjected to a cooling rate between 40-70° C./second, or subjected to the step cooling treatment, hot rolled steel sheet with a tensile strength greater than 590 MPa is produced. For hot rolled strip subjected to a cooling rate between 70-100° C./second, hot rolled steel sheet with a tensile strength greater than 690 MPa is produced. Also, the hot rolled steel sheet has a ferrite plus martensite microstructure free of pearlite and bainite.

Abstract: A process for producing high strength steel is provided. The process includes providing a steel slab having a chemical composition in weight percent within a range of 0.025-0.07 C, 1.20-1.70 Mn, 0.050-0.085 Nb, 0.022 max Ti, 0.065 max N, 0.0040 max S, 0.10-0.45 Si, 0.070 max P, with the balance being Fe and incidental impurities. The steel slab is soaked within a temperature range of 1150-1230° C., hot rolled using a roughing treatment in order to produce a transfer bar and further hot rolled using a finishing treatment in order to produce hot rolled strip. The hot rolled strip is cooled using a cooling rate between 10-100° C./second (sec) and coiled within a temperature range of 580-400° C. Finally, the coiled hot rolled strip has a yield strength of at least 80 ksi and a DWTT transition temperature equal or less than ?20° C.

Abstract: A process for manufacturing a cold rolled high strength dual phase steel. The process includes soaking a steel slab within a temperature range of 1200-1300° C., hot rolling the soaked steel slab in a roughing treatment and producing a transfer bar, and hot rolling the transfer bar in a finishing treatment and producing hot rolled strip. The hot rolled strip is cold rolled with at least a 55% reduction in thickness. The cold rolled sheet is intercritically annealed at a temperature between 790-840 ° C. and rapidly cooled to a temperature between 450-500 ° C. The rapidly cooled sheet has a ferrite plus martensite microstructure, a 0.2% yield strength of at least 550 MPa, a tensile strength of at least 980 MPa and a total elongation to failure of at least 10%.

Abstract: A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.

Abstract: Systems and methods are provided for analyzing unstructured time stamped data of a physical process in order to generate structured hierarchical data for a hierarchical time series analysis application. A plurality of time series analysis functions are selected from a functions repository. Distributions of time stamped unstructured data are analyzed to identify a plurality of potential hierarchical structures for the unstructured data with respect to the selected time series analysis functions.

Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.

Abstract: A caged phosphine product is provided which can act as a ligand to form a metal complex. The metal complex can be used as a catalyst.

Abstract: A machine and a method of applying a non-Newtonian liquid composition onto a surface in a controlled manner. The composition is held in a chamber at a controlled variable pressure and is dispensed through a slit die nozzle as controlled by a valve. Characteristics of the composition are empirically developed and provided to a logic control circuit to assure that the composition is dispensed on either the entire surface or in one or more precise locations.

Abstract: In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

Abstract: In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode.

Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion of the thickness of the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer imparts a stress to the first portion that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the thickness of the metal layer is then deposited over the stress-compensating layer.

Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.

Abstract: A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is etched to form a trench therein underlying the first opening. Silicon dioxide fills both the opening and the trench to form the shallow trench isolation structure, with the silicon dioxide in the opening exhibiting a negative taper angle to avoid formation of conductive stringers during subsequent process steps.

Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

Abstract: A bipolar device has at least one p? type layer of single crystal silicon carbide and at least one n? type layer of single crystal silicon carbide, wherein those portions of those stacking faults that grow under forward operation are segregated from at least one of the interfaces between the active region and the remainder of the device.

Abstract: Here, we demonstrate new material/structures for the photodetectors, using semiconductor material. For example, we present the Tunable Avalanche Wide Base Transistor as a photodetector. Particularly, SiC, GaN, AlN, Si and Diamond materials are given as examples. The desired properties of an optimum photodetector is achieved. Different variations are discussed, both in terms of structure and material.

Abstract: A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.

Abstract: One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.

Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.

Abstract: The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.