Patents by Inventor Randall C. Gray

Randall C. Gray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180356466
    Abstract: A circuit for diagnostic testing includes a current source coupled to a power source and configured to provide wetting current along a path to a load control switch, a current sensor connected in series with the current source along the path, the current sensor being configured to generate a current sensor signal indicative of a current level along the path, a voltage measurement unit having an input terminal coupled to a node along the path through which the wetting current flows to reach the load control switch, the voltage measurement unit being configured to detect a state of the load control switch based on a voltage at the node, and a controller coupled to the current sensor and the voltage measurement unit, the controller being configured to determine a wetting current diagnostic condition in accordance with the current level and the detected state.
    Type: Application
    Filed: August 14, 2018
    Publication date: December 13, 2018
    Inventors: William E. Edwards, Randall C. Gray, Anthony F. Andresen
  • Patent number: 10101395
    Abstract: A circuit for diagnostic testing includes a current source coupled to a power source and configured to provide wetting current along a path to a load control switch, a current sensor connected in series with the current source along the path, the current sensor being configured to generate a current sensor signal indicative of a current level along the path, a voltage measurement unit having an input terminal coupled to a node along the path through which the wetting current flows to reach the load control switch, the voltage measurement unit being configured to detect a state of the load control switch based on a voltage at the node, and a controller coupled to the current sensor and the voltage measurement unit, the controller being configured to determine a wetting current diagnostic condition in accordance with the current level and the detected state.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: October 16, 2018
    Assignee: NXP USA, INC.
    Inventors: William E. Edwards, Randall C. Gray, Anthony F. Andresen
  • Publication number: 20180031635
    Abstract: The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.
    Type: Application
    Filed: September 29, 2017
    Publication date: February 1, 2018
    Inventors: William E. EDWARDS, Anthony F. ANDRESEN, Randall C. GRAY
  • Patent number: 9778319
    Abstract: The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: October 3, 2017
    Assignee: NXP USA, INC.
    Inventors: William E. Edwards, Anthony F. Andresen, Randall C. Gray
  • Patent number: 9664729
    Abstract: Operation of an insulated gate bipolar transistor (IGBT) is monitored by an apparatus that has a capacitor connected between a collector of the IGBT and an input node. A processing circuit, coupled to the input node, responds to current flowing through the capacitor by providing an indication whether a voltage level at the collector is changing and the rate of that change. The processing circuit also employs the capacitor current to provide an output voltage that indicates the voltage at the IGBT collector.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: May 30, 2017
    Assignee: NXP USA, Inc.
    Inventors: Randall C. Gray, Ibrahim S. Kandah, Philipe J. Perruchoud, John M. Pigott, Thierry Sicard
  • Patent number: 9552890
    Abstract: The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. In such an embodiment the first diode effectively provides a bypass current path that can reduce the voltage across the antifuse when other antifuses are being programmed. As such, these embodiments can provide improved ability to tolerate programming voltages without damage or impairment of reliability.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: January 24, 2017
    Assignee: NXP USA, Inc.
    Inventors: John M. Pigott, Randall C. Gray
  • Patent number: 9466413
    Abstract: Embodiments of inductive communication devices include first and second galvanically isolated IC die and a dielectric structure. Each IC die has a coil proximate to a first surface of the IC die. The IC die are arranged so that the first surfaces of the IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. The dielectric structure is positioned within the gap directly between the first and second coils, and a plurality of conductive structures are positioned in or on the dielectric structure and electrically coupled with the second IC die. The conductive structures include portions configured to function as bond pads, and the bond pads may be coupled to package leads using wirebonds. During operation, signals are conveyed between the IC die through inductive coupling between the coils.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 11, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Fred T. Brauchler, John M. Pigott, Darrel R. Frear, Vivek Gupta, Randall C. Gray, Norman L. Owens, Carl E. D'Acosta
  • Publication number: 20160238658
    Abstract: A circuit for diagnostic testing includes a current source coupled to a power source and configured to provide wetting current along a path to a load control switch, a current sensor connected in series with the current source along the path, the current sensor being configured to generate a current sensor signal indicative of a current level along the path, a voltage measurement unit having an input terminal coupled to a node along the path through which the wetting current flows to reach the load control switch, the voltage measurement unit being configured to detect a state of the load control switch based on a voltage at the node, and a controller coupled to the current sensor and the voltage measurement unit, the controller being configured to determine a wetting current diagnostic condition in accordance with the current level and the detected state.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 18, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Randall C. Gray, Anthony F. Andresen
  • Patent number: 9385190
    Abstract: The embodiments described herein provide a semiconductor device layout and method that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes a plurality of deep trench isolation structures that define and surround a first plurality of first trench-isolated regions in the substrate, and further define a second plurality of second trench-isolated regions in the substrate. The first plurality of first trench-isolated regions is arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions. Likewise, the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: July 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: John M. Pigott, Brent D. Rogers, Randall C. Gray
  • Patent number: 9362987
    Abstract: Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: June 7, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Fred T. Brauchler, Randall C. Gray
  • Publication number: 20160131713
    Abstract: The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: William E. EDWARDS, Anthony F. ANDRESEN, Randall C. GRAY
  • Patent number: 9329237
    Abstract: A method of switch detection is disclosed that comprises, enabling a low power mode on a switch detection device, activating a first detection circuit for detecting, at a first expiration of a first polling time interval, a first switch state of a first switch having a first priority level, the first switch state including one of a first open state and a first closed state, comparing the detected first switch state with a prior first switch state, and activating a second detection circuit for detecting, at a second expiration of a second polling time interval, a second switch state of a second switch having a second priority level, the second switch including one of a second open state and a second closed state, and the second polling time interval being greater than the first polling time interval, and the second priority level being different from the first priority level.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Anthony F. Andresen, Randall C. Gray
  • Patent number: 9322870
    Abstract: A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 26, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, Randall C. Gray, Christopher B. Lesher
  • Patent number: 9285244
    Abstract: An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: March 15, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: John M. Pigott, Fred T. Brauchler, William E. Edwards, Mike R. Garrard, Randall C. Gray, John M. Hall
  • Publication number: 20150333805
    Abstract: Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 19, 2015
    Inventors: FRED T. BRAUCHLER, RANDALL C. GRAY
  • Publication number: 20150316602
    Abstract: Operation of an insulated gate bipolar transistor (IGBT) is monitored by an apparatus that has a capacitor connected between a collector of the IGBT and an input node. A processing circuit, coupled to the input node, responds to current flowing through the capacitor by providing an indication whether a voltage level at the collector is changing and the rate of that change. The processing circuit also employs the capacitor current to provide an output voltage that indicates the voltage at the IGBT collector.
    Type: Application
    Filed: January 9, 2013
    Publication date: November 5, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: RANDALL C. GRAY, IBRAHIM S. KANDAH, PHILIPE J. PERRUCHOUD, JOHN M. PIGOTT, THIERRY SICARD
  • Patent number: 9160423
    Abstract: Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: October 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Fred T. Brauchler, Randall C. Gray
  • Patent number: 9139155
    Abstract: A diagnostic circuit is provided that includes a FET having a source connected to a first node, a drain, and a gate; a first switch connecting a current-supply node to one of the gate and a second node; a second switch connecting the first node and the second node; a variable current source providing one of a drive current and a test current to the current-supply node; a fire current source configured to provide a fire current to the drain; an error-detecting circuit connected to the second node, a reference terminal, and an error node, the error-detecting circuit generating an error signal to the error node indicating whether an error-detecting parameter at the second node exceeds a reference parameter at the reference terminal; and a control circuit generating control signals to control the variable current source, and the first and second switches.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, Randall C. Gray
  • Publication number: 20150260548
    Abstract: An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described.
    Type: Application
    Filed: May 27, 2015
    Publication date: September 17, 2015
    Inventors: JOHN M. PIGOTT, FRED T. BRAUCHLER, WILLIAM E. EDWARDS, MIKE R. GARRARD, RANDALL C. GRAY, JOHN M. HALL
  • Publication number: 20150255537
    Abstract: The embodiments described herein provide a semiconductor device layout and method that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes a plurality of deep trench isolation structures that define and surround a first plurality of first trench-isolated regions in the substrate, and further define a second plurality of second trench-isolated regions in the substrate. The first plurality of first trench-isolated regions is arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions. Likewise, the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 10, 2015
    Inventors: John M. PIGOTT, Brent D. ROGERS, Randall C. GRAY