Abstract: A current-domain transmitter is configured to receive an input signal and provide a transmitted signal. The transmitter has a plurality of elements, operatively arranged between the input signal and the transmitted signal and configured to represent the input signal with respective electric currents whose respective current magnitudes are each substantially proportional to the input signal. The elements may include a current-steering digital-to-analog converter (DAC), a current mode filter (such as an LPF), a current mode mixer, and/or a current mode amplifier.

Abstract: The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential input coupled to a differential output of the pre-amplifier; and a replica comparator coupled to a common mode node of the pre-amplifier for adjusting a common mode of the pre-amplifier. The replica comparator provides a trip-point reference to set the output common mode of the pre-amplifier. This sets the output common mode of the pre-amplifier to the most sensitive region of the re-generated comparator.

Abstract: Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.

Abstract: A technique for generating carrier frequencies with fast hopping capability associated with multiband systems for ultra wideband applications. The technique employs a single VCO 20 that is locked in a PLL 30. The output of this VCO 20 is divided in the frequency domain. The divided frequencies thus obtained are combined in a single-sideband manner to obtain various other frequencies. The single-sideband combination requires open loop operations such as multiplication and addition or subtraction to implement, and hence is very fast. The VCO center frequency is not disturbed in the process. Since the required frequencies are generated in an open-loop fashion, instead of inside a PLL, the speed is increased by orders of magnitude.

Abstract: Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.

Abstract: The present invention pertains to a MOS type differential buffer circuit. The buffer proposed herein utilizes capacitive coupling to apply small AC signals to an amplifying current source to mitigate attenuation owing to body effect and output impedance, among other things, in an associated follower component. The proposed circuit does not, however, promote an increase in current and/or power dissipation. Additionally, the circuit allows a desired gain to be achieved while maintaining a relatively constant output impedance, compared to a simple differential source follower.

Abstract: A technique for generating carrier frequencies with fast hopping capability associated with multiband systems for ultra wideband applications. The technique employs a single VCO 20 that is locked in a PLL 30. The output of this VCO 20 is divided in the frequency domain. The divided frequencies thus obtained are combined in a single-sideband manner to obtain various other frequencies. The single-sideband combination requires open loop operations such as multiplication and addition or subtraction to implement, and hence is very fast. The VCO center frequency is not disturbed in the process. Since the required frequencies are generated in an open-loop fashion, instead of inside a PLL, the speed is increased by orders of magnitude.

Abstract: System and method for minimizing receiver sample timing error sensitivity. A preferred embodiment comprises matching received pulses to two pulses, a first pulse being advanced by a time offset and a second pulse being retarded by a time offset. Samples are created from the matching. The time offsets can be chosen based upon characteristics of the pulse itself. The samples can be combined to produce an output signal with less pronounced nulls that can reduce sensitivity to sample timing errors and a smoother overall profile that can enable gradient-based timing recovery scheme.

Abstract: A PHY entity for a UWB system utilizes the unlicensed 3.1-10.6 GHZ UWB band, as regulated in the United States by the Code of Federal Regulation, Title 47, Section 15. The UWB system provides a wireless pico area network (PAN) with data payload communication capabilities of 55, 80, 110, 160, 200, 320 and 480 Mb/s. The UWB system employs orthogonal frequency division multiplexing (OFDM) and uses a total of 122 sub-carriers that are modulated using quadrature phase shift keying (QPSK). Forward error correction coding (convolutional coding) is used with a coding rate of {fraction (11/32)}, ½, ⅝ and ¾.

Abstract: System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.

Abstract: A variable gain amplifier includes an input stage that receives an input signal and converts the input signal into a corresponding intermediate signal. An output stage provides an output signal based on the intermediate signal and a gain control signal, with feedback signal being provided to the input stage as a function of the gain control signal, so that the intermediate signal varies as a function of the input signal and the feedback signal. The linearity performance of the VGA is substantially constant at the output over the useful input range of signal amplitudes.

Abstract: System and method for combining maximizing a received signal in a multipath environment. A preferred embodiment comprises a rake receiver (for example, rake receiver 1100), created from switched capacitors, with N fingers. Each of the fingers is coupled to a signal input for a period of time to accumulate a charge on a storing capacitor (for example, storing capacitor 1115). The charges stored on the storing capacitors can then be read-out to produce a value. The rake receiver can implement either equal ratio combining or maximum gain combining to further improve received signal strength.

Abstract: System and method for analog signal generation and manipulation in an ultra-wideband (UWB) transmitter. A preferred embodiment comprises a digital portion 305 of an UWB transmitter (for example, transmitter 300), which is responsible for encoding a data stream to be transmitted, and an analog portion 330. The analog portion 330 creates a stream of short duration pulses from the encoded data stream and then filters the stream of short duration pulses. To simplify the generation of the short duration pulses, a quantized representation of the short duration pulse is used. The quantized representation is created via the use of control signals that by coupling differential amplifiers together (such as amplifier 611), generate a voltage drop across a resistor (such as resistor 619) and hence, a current.

Abstract: System and method for maximizing a signal strength of a received signal pulse. A preferred embodiment comprises a self-adjusting correlator/integrator (for example, correlator/integrator 325) that uses no historical timing information. The self-adjusting correlator/integrator uses a plurality of simple correlators/integrators (for example, correlator/integrator 805) which are configured to process a received signal at various times surrounding the signal pulse's expected arrival. A comparator (for example, comparator 820) selects an output of the simple correlators/integrators with greatest magnitude.

Abstract: A buffer circuit includes a differential pair output switch having an additional NPN device and resistor operational to increase the common mode output voltage of the buffer during a switching event, such that the voltage movement at the common emitter node of the differential pair output switch for the buffer circuit is decreased to substantially reduce distortion of an output signal associated with a DAC that employs the buffer circuit.

Abstract: A speed-up mode control system is operative to generate a speed-up mode signal based on a gain control signal from associated digital circuitry. The speed-up mode signal controls electronics associated with one or more amplifiers to facilitate settling time of an output signal of the amplifier(s) that occurs when the gain of the amplifier changes. The gain control signal also can be delayed to provide a delayed version of the gain control signal for controlling gain of the amplifier(s).

Abstract: A variable gain amplifier includes an input stage that receives an input signal and converts the input signal into a corresponding intermediate signal. An output stage provides an output signal based on the intermediate signal and a gain control signal, with feedback signal being provided to the input stage as a function of the gain control signal, so that the intermediate signal varies as a function of the input signal and the feedback signal. The linearity performance of the VGA is substantially constant at the output over the useful input range of signal amplitudes.

Abstract: For simulating electrostatic discharge and latch-up in semiconductor devices, the disclosed system and method for extracting parasitic devices combine input data from device layout, technology rules and doping profiles in order to extract netlists, element location and substrate resistance, analyze the layout for parasitic device formation, store these lists in a verification data base, translate the data base into a specific format, and finally output lists of ESD- and latch-up-sensitive elements and their locations in a specific format such as SPICE format.

Abstract: A buffer circuit includes a differential pair output switch having an additional NPN device and resistor operational to increase the common mode output voltage of the buffer during a switching event, such that the voltage movement at the common emitter node of the differential pair output switch for the buffer circuit is decreased to substantially reduce distortion of an output signal associated with a DAC that employs the buffer circuit.

Abstract: A full-wave rectifier circuit (500) includes a cross-coupled differential pair circuit (501) coupled to a bias circuit (510). At least one constant current source (512, 514) couples to the base of each transistor (506, 508) in the cross-coupled pair circuit (501). A differential pair of transistors (502, 504) drive the cross-coupled pair circuit (501). Cross-coupled devices (506, 508) are used as positive feedback to increase gain for small amplitude signals and to degenerate the devices (502, 504) of the full-wave rectifier. Using this design very precise rectification can be achieved even for &thgr;i<VT. Specifically, the bias circuit (510) includes a current source which supplies &agr; multiplied by the current supplied by the current source (512, 514) connected to the base of the transistors (506, 508) in the cross-coupled pair circuit (501). By choosing an appropriate value of &agr;, a unity magnitude slope close to the origin is achieved.