Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively. The bias circuit (305) is configured to eliminate base shot-noise of the mirror transistor (Q1) which generates the amplification. The bias circuit (305) in accordance with the present invention also eliminates the noise of the bias resistor (Rx1) that is included within the bias circuit (305). Specifically, the bias circuit (305) includes a current reference source (Iref) and an emitter follower circuit (315) connected to a current mirror circuit (Q1, Q2, Rx2) that connects to a bias resistor (Rx1). This bias circuit (305) can be implemented in a wide-class of single-ended circuits.

Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively.

Abstract: A quadrature output oscillator device (22) includes a first voltage controlled oscillator (40) and a second voltage controlled oscillator (44). The second voltage controlled oscillator (44) generates a first output (C) and a second output (D) to drive a first amplifier (42). The second output (D) of the second voltage controlled oscillator (44) is a quadrature-phase signal component output (Q) of the quadrature output oscillator device (22). The first voltage controlled oscillator (40) generates a first output (A) and a second output (B) to drive a second amplifier (46). The second output (B) of the first voltage controlled oscillator (40) is an in-phase signal component output (I) of the quadrature output oscillator device (22). The first amplifier (42) generates feedback signals for the first output (A) and the second output (B) of the first voltage controlled oscillator (40).

Abstract: For simulating electrostatic discharge and latch-up in semiconductor devices, the disclosed system and method for extracting parasitic devices combine input data from device layout, technology rules and doping profiles in order to extract netlists, element location and substrate resistance, analyze the layout for parasitic device formation, store these lists in a verification data base, translate the data base into a specific format, and finally output lists of ESD- and latch-up-sensitive elements and their locations in a specific format such as SPICE format.

Abstract: In a pipelined analog-to-digital converter (ADC) having an analog input signal and a digital output signal, and having a plurality of pipelined stages, each such stage having an analog input, an analog output comprising a residue voltage, and a digital output, the stage including a digital-to-analog converter substage having a plurality of capacitors and which are used in a sample-and-hold function and shuffled according to a predetermined procedure, a method for reducing noise generated from the shuffling when the capacitors are mismatched. The method includes the following steps. First, an estimation model is provided of the noise generated from the shuffling. The estimation model includes factors corresponding to mismatches of the capacitors. Mismatches among capacitors in the stage are estimated, based on the monitoring of an output parameter of the stage. A cancellation factor is generated by applying the mismatch estimations to the estimation model.

Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively. The bias circuit (305) is configured to eliminate base shot-noise of the mirror transistor (Q1) which generates the amplification. The bias circuit (305) in accordance with the present invention also eliminates the noise of the bias resistor (Rx1) that is included within the bias circuit (305). Specifically, the bias circuit (305) includes a current reference source (Iref) and an emitter follower circuit (315) connected to a current mirror circuit (Q1, Q2, Rx2) that connects to a bias resistor(Rx1). This bias circuit (305) can be implemented in a wide-class of single-ended circuits.

Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively.

Abstract: A receiver (54) comprising an input for receiving an RF signal (FIG. 7) centered at a first frequency and having a bandwidth. The receiver also comprises a first mixer (62) for producing a first output signal. The first output signal results from mixing the RF signal with a signal having an energy spreading portion (p(t)) and a down-converting portion (c(t)). Moreover, this first output signal comprises a self-mixing DC signal (c(t)p(t) self-mixing DC component) and a down-converted and energy spread RF signal (FIG. 11). The receiver further comprises a second mixer (70) for producing a second output signal by mixing a signal responsive to the first output signal with the energy spreading portion of the signal. The second output signal comprises two signals, namely: (1) a baseband signal (down-converted RFA1) responsive to the down-converted and energy spread RF signal; and (2) a portion of the spread DC signal (spread DC).

Abstract: A two stage low noise amplifier (10) includes a first stage (12) and a second stage (14). The first stage (12) receives an input signal (VIN), performs single to differential conversion on the input signal (VIN), and generates an input differential signal (VA and VB) therefrom. A bias level of the input differential signal (VA and VB) may be adjusted to an optimal bias point of the second stage (14). The first stage (12) provides the input differential signal (VA and VB) to the second stage (14) And provides image rejection without any loss in amplifier gain. The second stage (14) performs image rejection on the input differential signal (VA and VB) and generates an output differential signal (V+ and V−) therefrom. The first stage (12) and stage (14) include a tuning circuit to adjust a center operating frequency of the amplifier (10). The first stage (12) and the second stage (14) receive control signals from a control bus (16) in order to adjust the center operating frequency.

Abstract: A full-wave rectifier circuit (500) includes a cross-coupled differential pair circuit (501) coupled to a bias circuit (510). At least one constant current source (512, 514) couples to the base of each transistor (506, 508) in the cross-coupled pair circuit (501). A differential pair of transistors (502, 504) drive the cross-coupled pair circuit (501). Cross-coupled devices (506, 508) are used as positive feedback to increase gain for small amplitude signals and to degenerate the devices (502, 504) of the full-wave rectifier. Using this design very precise rectification can be achieved even for &thgr;i<VT.

Abstract: A radio such as a frequency division duplex (FDD) radio (100) has a first local oscillator (LO1I and LO1Q) that is set to coincide with the transmitter section's (126) center frequency or a sub-harmonic thereof. In this way, after the first down-conversion, the transmit interferer is converted to DC, where it can be effectively removed using a simple high-pass filter (110, 112) such as a DC blocking capacitor. Image rejection is achieved by the use of a two-step down-conversion approach that uses quadrature local oscillators to implement a single-sideband down-converter.

Abstract: A two stage low noise amplifier (10) includes a first stage (12) and a second stage (14). The first stage (12) receives an input signal (VIN), performs single to differential conversion on the input signal (VIN), and generates an input differential signal (VA and VB) therefrom. A bias level of the input differential signal (VA and VB) may be adjusted to an optimal bias point of the second stage (14). The first stage (12) provides the input differential signal (VA and VB) to the second stage (14) without any loss in amplifier gain. The second stage (14) performs image rejection on the input differential signal (VA and VB) and generates an output differential signal (V+ and V−) therefrom. The first stage (12) and the second stage (14) include a tuning circuit to adjust a center operating frequency of the amplifier (10). The first stage (12) and the second stage (14) receive control signals from a control bus (16) in order to adjust the center operating frequency.