Patents by Inventor Ranko Scepanovic
Ranko Scepanovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7739575Abstract: An improvement to an arithmetic unit of a low-density parity-check decoder, where the arithmetic unit has a pipelined architecture of modules. A first module calculates a difference between absolute values of md_R and md_g_in, and passes the result to a first Gallager module. The first Gallager module converts this value from a p0/p1 representation to a 2*p0?1 representation, and passes the result to a second module. The second module selectively adjusts the result of the previous module based on the sign values of md_g_in and md_R, and passes one of its outputs to a third module (the other two outputs, loc_item_out and hard_out, are not a part of the pipeline). The third module calculates a new md_g value by adding the result of the second module and loc_item_in, and passes this result to a fourth module. The fourth module separates a sign and an absolute value of the new md_g, and passes the result to a second Gallager module.Type: GrantFiled: January 24, 2007Date of Patent: June 15, 2010Assignee: LSI CorporationInventors: Alexander Andreev, Vojislav Vukovic, Ranko Scepanovic
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Publication number: 20100023904Abstract: A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.Type: ApplicationFiled: July 23, 2009Publication date: January 28, 2010Applicant: LSI CORPORATIONInventors: Alexandre Andreev, Andrey Nikitin, Ranko Scepanovic, Igor A. Vikhliantsev
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Publication number: 20090316507Abstract: The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address signal, an initial state parameter, a target state parameter, a first port enable signal, a second port enable signal, a write enable signal, a data input signal, a first location signal and a second location signal. The address locator circuit may be configured to generate the first location signal and the second location signal in response to the first port address signal, the second port address signal and the current address signal.Type: ApplicationFiled: June 20, 2008Publication date: December 24, 2009Inventors: Alexandre E. Andreev, Anatoli A. Bolotov, Ranko Scepanovic
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Publication number: 20090309770Abstract: Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network.Type: ApplicationFiled: June 13, 2008Publication date: December 17, 2009Inventors: Alexander Andreev, Sergey Gribok, Oleg Izyumin, Ranko Scepanovic, Igor Vikhliantsev, Vojislav Vukovic
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Publication number: 20090281969Abstract: An arbitrary function may be represented as an optimized decision tree. The decision tree may be calculated, pruned, and factored to create a highly optimized set of equations, much of which may be represented by simple circuits and little, if any, complex processing. A circuit design system may automate the decision tree generation, optimization, and circuit generation for an arbitrary function. The circuits may be used for processing digital signals, such as soft decoding and other processes, among other uses.Type: ApplicationFiled: May 9, 2008Publication date: November 12, 2009Applicant: LSI CorporationInventors: Alexander Andreev, Vojislav Vukovic, Ranko Scepanovic
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Patent number: 7584442Abstract: A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.Type: GrantFiled: December 9, 2005Date of Patent: September 1, 2009Assignee: LSI CorporationInventors: Alexandre Andreev, Andrey Nikitin, Ranko Scepanovic, Igor A. Vikhliantsev
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Publication number: 20090187873Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Applicant: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Publication number: 20090133003Abstract: A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.Type: ApplicationFiled: November 21, 2007Publication date: May 21, 2009Applicant: LSI CorporationInventors: Alexander E. Andreev, Anatoli A. Bolotov, Ranko Scepanovic
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Publication number: 20090094571Abstract: The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.Type: ApplicationFiled: December 9, 2008Publication date: April 9, 2009Inventors: Andrey A. Nikitin, Alexander E. Andreev, Ranko Scepanovic
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Patent number: 7512918Abstract: A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.Type: GrantFiled: August 17, 2005Date of Patent: March 31, 2009Assignee: LSI CorporationInventors: Alexander Andreev, Andrey Nikitin, Ranko Scepanovic
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Patent number: 7472358Abstract: The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.Type: GrantFiled: October 27, 2005Date of Patent: December 30, 2008Assignee: LSI CorporationInventors: Andrey A. Nikitin, Alexander E. Andreev, Ranko Scepanovic
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Publication number: 20080295044Abstract: A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.Type: ApplicationFiled: August 5, 2008Publication date: November 27, 2008Applicant: LSI CorporationInventors: Alexandre Andreev, Andrey Nikitin, Ilya V. Neznanov, Ranko Scepanovic
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Patent number: 7424687Abstract: A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.Type: GrantFiled: November 16, 2005Date of Patent: September 9, 2008Assignee: LSI CorporationInventors: Alexandre Andreev, Andrey Nikitin, Ilya V. Neznanov, Ranko Scepanovic
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Patent number: 7415686Abstract: A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each memory module has a capacity of C bits addressed by the address input.Type: GrantFiled: December 19, 2005Date of Patent: August 19, 2008Assignee: LSI CorporationInventors: Alexander Andreev, Anatoli A. Bolotov, Ranko Scepanovic
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Patent number: 7415691Abstract: The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a sequence of commands and data described by a flowchart includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A module (e.g., a CKD, or the like) is generated to include the ROM, wherein the module receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.Type: GrantFiled: July 20, 2004Date of Patent: August 19, 2008Assignee: LSI CorporationInventors: Alexander E. Andreev, Andrey A. Nikitin, Ranko Scepanovic
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Publication number: 20080178057Abstract: An improvement to an arithmetic unit of a low-density parity-check decoder, where the arithmetic unit has a pipelined architecture of modules. A first module calculates a difference between absolute values of md_R and md_g_in, and passes the result to a first Gallager module. The first Gallager module converts this value from a p0/p1 representation to a 2*p0?1 representation, and passes the result to a second module. The second module selectively adjusts the result of the previous module based on the sign values of md_g_in and md_R, and passes one of its outputs to a third module (the other two outputs, loc_item_out and hard_out, are not a part of the pipeline). The third module calculates a new md_g value by adding the result of the second module and loc_item_in, and passes this result to a fourth module. The fourth module separates a sign and an absolute value of the new md_g, and passes the result to a second Gallager module.Type: ApplicationFiled: January 24, 2007Publication date: July 24, 2008Applicant: LSI LOGIC CORPORATIONInventors: Alexander Andreev, Vojislav Vukovic, Ranko Scepanovic
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Patent number: 7389484Abstract: A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed recursively based on a comparison of at least one of a capacity and a width of the object and that of the respective object location: (1) do nothing; (2) reconfigure the object to have a different capacity and/or width; and (3) split the object into two or more separate objects. The recursion is repeated for each reconfigured object and each separated object.Type: GrantFiled: November 16, 2005Date of Patent: June 17, 2008Assignee: LSI CorporationInventors: Alexandre Andreev, Andrey Nikitin, Ilya V. Neznanov, Ranko Scepanovic
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Patent number: 7340706Abstract: The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the OPC mask. The method also includes classifying each cell of at least one of the target layer and the OPC mask layer as either repeating or non-repeating, and for each repeating cell, recognizing geometric points in the target layer to determine quality measuring groups. The method also includes simulating the OPC mask layer based on the quality measuring groups, measuring edge placement errors (EPEs) based on at least one of the geometric points, and providing an EPE layer representing EPEs greater than an EPE threshold.Type: GrantFiled: September 30, 2005Date of Patent: March 4, 2008Assignee: LSI Logic CorporationInventors: Ilya Golubtsov, Stanislav V. Aleshin, Ranko Scepanovic, Sergei Rodin, Marina Medvedeva, Sergey V. Uzhakov, Evgueny E. Egorov, Nadya Strelkova
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Publication number: 20080049719Abstract: A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.Type: ApplicationFiled: October 25, 2007Publication date: February 28, 2008Applicant: LSI CorporationInventors: Alexander Andreev, Anatoli Bolotov, Ranko Scepanovic
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Publication number: 20080046764Abstract: A method of storing sensitive data by generating randomization values, transforming the sensitive data and the randomization values into a result, and storing separate portions of the result on at least two storage devices, such that the sensitive data cannot be disclosed if any one of the storage devices is compromised.Type: ApplicationFiled: January 8, 2007Publication date: February 21, 2008Applicant: LSI LOGIC CORPORATIONInventors: Mikhail Grinchuk, Anatoli Bolotov, Ranko Scepanovic, Robert Waldron