Abstract: An original netlist is transformed to one employing universal gates. A negation net is created for each net coupled to an input or output of each gate and an input of each inverter in the original net. Each gate is removed from the original netlist and a universal gate is inserted so that the nets previously coupled to the inputs and output of the removed gate and a negation of those nets are coupled to the inputs and outputs of the inserted universal gate in a selected arrangement. Each inverter is removed from the original netlist and the net previously coupled to the input of the inverter is negated. A universal gate comprises gates performing anding and oring functions whose inputs and outputs are selectively coupled to the nets of the original netlist, and their negations.

Abstract: The present invention is directed to a system and method for providing multidirectional routing. The present invention may provide an arbitrary number of routing layers and an arbitrary direction on each of those layers to provide a smaller die size and to reduce power consumption by providing more flexibility for net routing directions.

Abstract: The present invention is directed to a simplification method for an arbitrary library. In aspects of the present invention, the method does not rely on specific properties of the library elements and has linear complexity. The present invention may be implemented based on a symbolic simulation in an alphabet which contains 0, 1, symbols of variables, and negations of the variables' symbols. In an aspect of the present invention, a method for reducing redundancy in a simulation through use of a symbolic simulation utilizing an arbitrary library includes receiving a set A of values, the set A including input variables which are elements of the set A. Symbols of the input variables are constructed in which like and similar variables share a like symbol and a similar symbol respectively. A table of output values computed from a table of a Boolean operator employing the constructed symbols of the input variable is formed, the constructed symbols formed to reduce redundancy.

Abstract: A memory module is formed on an integrated circuit by arranging memory cells in columns, and routing signal wires from module pins at an edge of the module to respective memory cells. The module pins are optimally positioned relative to the memory cells, and routing wires extend from the pins along routing lines to the cells. Buffer channels are defined between memory cells and orthogonal to the columns, and buffers are selectively inserted into the routing wires in the buffer channels by placing a plurality of buffers in each buffer channel. Signal wires to be buffered at a buffer channel are identified, and the signal wires are routed through each buffer channel so that (i) a signal wire to be buffered is re-routed to an input and output of a buffer, and (ii) all other signal wires are routed along their respective routing lines.

Abstract: A method of calculating skews for memory cells and flip-flops in a circuit design to reduce peak power includes receiving a circuit design containing memory cells and other clocked cells; constructing a first graph that includes a union of all inputs, vertices representative of the memory cells and the other clocked cells, a union of all outputs, and edges between the vertices each having a length equal to a delay between corresponding vertices minus a clock period; constructing a second graph having vertices representative of only the memory cells and corresponding edges such that the maximum length between any two corresponding vertices is less than zero; calculating a skew for each of the memory cells from the second graph; constructing a third graph from the first graph by merging the vertices of the memory cells into a single vertex; calculating a skew for each of the other clocked cells from the third graph; normalizing each skew calculated for the other clocked cells; recalculating the skew for each of

Abstract: A longest common subprefix of two binary words p1 and p2 is identified based on bit strings ip1 and ip2 which are extensions of p1 and p2, and binary words n1 and n2 that define the length of p1 and p2. The bit strings and words are processed to set a “greater” output if p1>p2 and to set an “equal” output if p1=p2. A mask having a consecutive string of most significant bits having a first logical value is constructed to identify the matching subprefixes of p1 and p2.

Abstract: A bus is defined on a core of an integrated circuit. Routing lines are defined through the core, and net wires are routed through the core along respective routing lines. Buffer columns are defined in the core across a plurality of nets, and buffers are placed in the buffer columns so that an input and output to a respective buffer are on different routing lines. The buffers have at least one free routing line and the net wires are redistribution across the buffer so that (i) the net wire to be buffered is re-routed to the input and output of the buffer, (ii) the net wires on routing lines containing the input and output of the buffer are re-routed to the routing line of the net wire to be buffered and the free routing line, and (iii) all other net wires are routed along their respective routing lines.

Abstract: A controller for repairing a redundant memory circuit includes a fault storage matrix for mapping a repair solution, a plurality of registers for storing row and column coordinates of the repair solution, and a repair solution calculator coupled to the plurality of registers and the fault storage matrix for receiving an x-coordinate and a y-coordinate of a defective memory cell in the redundant memory circuit and for determining whether a repair solution may be found from the fault storage matrix.

Abstract: A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes exploding calls on an element list to generate an expanded element list, defining a local cover area for each call on the expanded element list, classifying congruent local cover areas into corresponding groups, and performing an OPC procedure for one local cover area in each group.

Abstract: The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.

Abstract: A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.

Abstract: Entries are added or deleted on a search tree starting with a selected vertex on an identified level of the tree. If the level of the selected vertex is the bottom level the entry is inserted to or deleted from the selected vertex. If the level of the selected vertex is not the bottom level, the entries on the child vertices of the selected vertex are redistributed so that the child vertex having a maximal index contains a predetermined number of entries. If the level of the child vertex is the bottom level the entry is inserted to or deleted from the child vertex. Otherwise, the process repeats, using the child and grandchild vertices, until the correct level is reached.

Abstract: A method of calculating skews for memory cells and flip-flops in a circuit design to reduce peak power includes receiving a circuit design containing memory cells and other clocked cells; constructing a first graph that includes a union of all inputs, vertices representative of the memory cells and the other clocked cells, a union of all outputs, and edges between the vertices each having a length equal to a delay between corresponding vertices minus a clock period; constructing a second graph having vertices representative of only the memory cells and corresponding edges such that the maximum length between any two corresponding vertices is less than zero; calculating a skew for each of the memory cells from the second graph; constructing a third graph from the first graph by merging the vertices of the memory cells into a single vertex; calculating a skew for each of the other clocked cells from the third graph; normalizing each skew calculated for the other clocked cells; recalculating the skew for each of

Abstract: A memory module is formed on an integrated circuit by arranging memory cells in columns, and routing signal wires from module pins at an edge of the module to respective memory cells. The module pins are optimally positioned relative to the memory cells, and routing wires extend from the pins along routing lines to the cells. Buffer channels are defined between memory cells and orthogonal to the columns, and buffers are selectively inserted into the routing wires in the buffer channels by placing a plurality of buffers in each buffer channel. Signal wires to be buffered at a buffer channel are identified, and the signal wires are routed through each buffer channel so that (i) a signal wire to be buffered is re-routed to an input and output of a buffer, and (ii) all other signal wires are routed along their respective routing lines.

Abstract: A bus is defined on a core of an integrated circuit. Routing lines are defined through the core, and net wires are routed through the core along respective routing lines. Buffer columns are defined in the core across a plurality of nets, and buffers are placed in the buffer columns so that an input and output to a respective buffer are on different routing lines. The buffers have at least one free routing line and the net wires are redistribution across the buffer so that (i) the net wire to be buffered is re-routed to the input and output of the buffer, (ii) the net wires on routing lines containing the input and output of the buffer are re-routed to the routing line of the net wire to be buffered and the free routing line, and (iii) all other net wires are routed along their respective routing lines.

Abstract: A process for re-designing IC chips by altering the positions of cells from a first to a second IC chip layout. An x,y grid is established for the first and second IC layouts such that each cell has identifying x,y coordinates in the first layout. Columns are established in the second layout based on the bounds of the second layout in the x-direction. The cells are sorted to the columns in the order of cell x-coordinates to establish new x-coordinates for each cell based on the x-coordinates of the respective column. The cells are sorted in each column to establish y-coordinates for each cell based on the height of the cells in the column and the height of the column.

Abstract: A method of constructing a circuit for a Boolean function includes receiving as input a Boolean function of a number n of input variables wherein the number n of input variables may be varied over a range; generating at least two intermediate functions comprising sub-functions of the Boolean function wherein zero or one is substituted for all but two of the number n of input variables; and generating a selected output of the Boolean function of the number n of input variables from only two of the intermediate functions.

Abstract: A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.

Abstract: A search engine architecture substitutes short indices for large data widths, thereby reducing widths required for input to and output from the search engine. The search engine system comprises a search engine responsive to an input address to access an index in the search engine. The index has a width no greater than logarithm on base 2 of the search engine capacity, thereby permitting the search engine to be embodied in an IC chip of reduced area. A driver responds to input commands and to the search engine status to manage indices in the search engine and enable the memory to access its addressable locations based on indices in the search engine.

Abstract: A method of changing a number of entries in a sorted binary tree includes selecting a protocol parameter P for determining a tradeoff between memory utilization and required execution time; defining a minimum number of entries and a maximum number of entries in each vertex of the sorted binary tree as a function of the protocol parameter P; if inserting an entry into a bottom vertex of the sorted binary tree exceeds the maximum number of entries in the bottom vertex, then redistributing entries in the sorted binary tree until no bottom vertex has more than the maximum number of entries and no fewer than the minimum number of entries or creating a new bottom vertex in the sorted binary tree and redistributing entries in the sorted binary tree until no bottom vertex has more than the maximum number of entries or fewer than the minimum number of entries; if deleting an entry from the bottom vertex results in fewer than the minimum number of entries, then redistributing entries in the sorted binary tree until no