Abstract: The present invention is directed to a simplification method for an arbitrary library. In aspects of the present invention, the method does not rely on specific properties of the library elements and has linear complexity. The present invention may be implemented based on a symbolic simulation in an alphabet which contains 0, 1, symbols of variables, and negations of the variables' symbols. In an aspect of the present invention, a method for reducing redundancy in a simulation through use of a symbolic simulation utilizing an arbitrary library includes receiving a set A of values, the set A including input variables which are elements of the set A. Symbols of the input variables are constructed in which like and similar variables share a like symbol and a similar symbol respectively. A table of output values computed from a table of a Boolean operator employing the constructed symbols of the input variable is formed, the constructed symbols formed to reduce redundancy.

Abstract: The present invention is directed to fast flexible search and edit pipeline separation. A system suitable for providing a search may include a central controller and at least one search engine. The central controller is suitable for implementing search and edit operations. The at least one search engine is communicatively coupled to the central controller. The central controller performs parallel execution of a search operation and an edit operation through utilization of the at least one search engine.

Abstract: The present invention is a method and apparatus for optimizing the design of a combinational circuit. The method includes constructing a circuit sheaf for the combinational circuit and then performing vector optimization with domination. In the preferred embodiment, a complete BDD B is determined and, from that, a list of F-sets is computed. If the combinational circuit includes cells other than NOT, AND and XOR cells, the circuit is first transformed such that it only has those types of cells.

Abstract: The present invention is directed to a system and method for providing multidirectional routing. The present invention may provide an arbitrary number of routing layers and an arbitrary direction on each of those layers to provide a smaller die size and to reduce power consumption by providing more flexibility for net routing directions.

Abstract: A subprefix is selected from a prefix search tree that has a longest match to a search prefix. A binary search prefix is input to the root vertex of the tree, and is compared to the prefixes in selected hierarchy vertices. A bit is set in a search mask based on a least significant bit of a bit string in the search prefix that matches a longest bit string in a prefix in each vertex. A longest matching subprefix is selected from a string of most significant bits of the search prefix based on the lowest significant bit set in the search mask. A prefix mask is also provided for each prefix in the tree, and is useful in connection with construction of the search mask.

Abstract: A binary search tree is structured so that keys or addresses associated with data in the bottom vertices are arranged in a predetermined order, such as ascending key address order. The root vertex and each hierarchy vertex contains the lowest value key from each child vertex and are thus similarly arranged by key value order. Each vertex of each level contains at least k and no more than 2k−1 keys, where k is an integer ≦2 and is constant for all vertices of a given level, but may vary between levels. The result is a structured tree having equal path lengths between the root vertex and each bottom vertex for search purposes. Keys are deleted and inserted to the bottom vertices by restructuring the tree under control of computer instructions.

Abstract: Constant pins are determined in a combinational circuit by associating an input of a combinational circuit with a first variable and a second variable, with the second variable being the complement of the first variable. For a first logical cell interconnected to such input, a first mathematical representation and a second mathematical representation are computed. The first mathematical representation is a function of the operation of the first logical cell and a function of the first variable, and the second mathematical representation is a function of the operation of the first logical cell and a function of the second variable. A determination is then made as to whether one of the first and second mathematical representations is equal to a constant.

Abstract: A metal wire for a feature of a cell is extended using a grid based on a metal layer of the cell. Each grid element is assigned an “F” designator representing the metal wire being extended, an “E” designator representing blockages to extension of the metal wire, such as metal wires of other features, or a “U” designator representing grid elements that are neither F-designated, nor E-designated grid elements. U-designated grid elements that are neighbors to E-designated grid elements are identified. A minimum length path is defined through the U-designated grid elements that are not neighbors to E-designated grid elements between the cell boundary and a F-designated grid element.

Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.

Abstract: The present invention involves a method for determining constant pins in a combinational circuit. The method comprises the steps of associating an input of a combinational circuit with a first variable and a second variable, wherein said second variable is the compliment of said first variable, computing for a first logical cell interconnected to said input a first canonical representation, wherein said first canonical representation is a function of the operation of said first logical cell and a function of said first value, computing for said first logical cell a second canonical representation, wherein said second canonical representation is a function of the operation of said first logical cell and a function of said second value, determining whether one of said first and second canonical representations is equal to zero.

Abstract: A minimum core size of an integrated circuit chip is estimated for given parameters of an existing technology. The average wire length for the nets is calculated, and the centers of each cell are assigned to x,y coordinates to minimize wire length. The widths of routing channels between consecutive columns, and their associated core sizes are estimated based on the cell placement and the existing technology parameters. The minimum core size is identified from the estimated core sizes.

Abstract: The present invention involves a method for reducing delay of a net. The method includes constructing a time-space grid, said time-space grid corresponding to a net, passing a wave through the time-space grid, said wave having a wave value, and inserting a buffer at a point on said time-space grid where insertion of the buffer increases a wave value. The buffer can be a negative buffer or positive buffer. Generally, a second wave is passed through the time-space grid simultaneously with the first wave. Typically, the second wave and the first wave are inverted.

Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.

Abstract: A physical design automation system produces an optimal placement of microelectronic components or cells on an integrate circuit chip. An initial population of possible cell placements is generated, and repeatedly altered using simulated on or other fitness improvement algorithm to progressively increase the fitnesses (decrease the costs) of the placements. After each alteration step, the fitnesses of the placements are calculated, and less fit placements are discarded in favor of more fit placements. After a termination criterion is reached, the placement having the highest fitness is designated as the optimal placement. Two or more fitness improvement algorithms are available, and are optimally switched from one to the other in accordance with an optimization criterion to maximize convergence of the placements toward the optimal configuration.

Abstract: An RTL description, such as a Verilog description, of an integrated circuit is derived from a C/C++ description by defining the integrated circuit as a generalized multiplexer having outputs and two groups of input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn in which each variable X1, X2, . . . , Xs, is fixed and no output depends on more than one variable of Y1, Y2, . . . , Yn. An output vector is constructed by Exclusive-OR operations to find an index j for UU1=(BIT(0,j), BIT(1,j), . . . , BIT(K−1),j)). The Verilog description of the circuit is a function of the solution of the output vector, or a constant.

Abstract: A test signal is propagated through at least a portion of the circuit from a respective input. The test signal is based on a row of a k-wise, &egr;-discrepant matrix. Cells are identified whose outputs have a constant response to the test signal and the inputs of the identified cells are combined with the inputs of the circuit. The process is iteratively repeated until the output of the circuit is reached. The circuit inputs and inputs of identified cells are selected as test points.

Abstract: A process for re-designing IC chips by altering the positions of cells from a first to a second IC chip layout. An x,y grid is established for the first and second IC layouts such that each cell has identifying x,y coordinates in the first layout. Columns are established in the second layout based on the bounds of the second layout in the x-direction. The cells are sorted to the columns in the order of cell x-coordinates to establish new x-coordinates for each cell based on the x-coordinates of the respective column. The cells are sorted in each column to establish y-coordinates for each cell based on the height of the cells in the column and the height of the column.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.

Abstract: A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.