Abstract: A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.

Abstract: In one embodiment, a pipelined processor includes a reset unit that provides an output reset signal to at least one stage of the pipeline. The reset unit is adapted to detect at least a hard reset request, a soft reset request and an emulation reset request. The pipeline comprises N stages and the reset unit asserts the reset signal for at least N cycles of a clock after the reset request has been cleared. Each stage if the pipeline has a storage circuit for storing a corresponding valid bit. At least one of the storage circuits is cleared in response to the reset signal. In addition, the reset unit handles the reset request as a reset event having an assigned priority.

Abstract: A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.

Abstract: In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of the execution pipeline. The MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.

Abstract: In an embodiment, a processor may be operable in a user mode and in a supervisor mode. The processor may initialize hardware loops in the user mode by loading a top instruction address in a LOOP_TOP register and a bottom instruction address in a LOOP_BOT register. A user program could conceivably gain access to the supervisor mode by loading the target address of an event service routine, in the supervisor instruction address space, in the LOOP_BOT register and an address in the user instruction address space in the LOOP_TOP register. If the event occurred in the supervisor mode, the program flow could branch to the address in the LOOP_TOP register, giving the user program control in the supervisor mode. To avoid this potential security hazard, the processor may disable hardware loop operations when the processor exits the user mode.

Abstract: In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.

Abstract: In one embodiment, a watchpoint engine generates watchpoints for code developed for a complex integrated circuit device such as a pipelined processor.

Abstract: In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.

Abstract: In one embodiment, a programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The first and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.

Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).

Abstract: In one embodiment, a programmable processor is adapted to include a speculative count register. The speculative count register may be loaded with data associated with an instruction before the instruction commits. However, if the instruction is terminated before it commits, the speculative count register may be adjusted. A set of counters may monitor the difference between the speculative count register and its architectural counterpart.

Abstract: In one embodiment, a programmable processor includes a pipeline having a number of stages. A stall controller is adapted to pre-detect a hazard condition within one of the stages of the pipeline and synchronously stall another stage of the pipeline. The stall controller generates additional stall signals in order to stall other stages in the pipeline.