Patents by Inventor Ravishankar Iyer

Ravishankar Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9852002
    Abstract: Systems, methods, and apparatuses for resource monitoring identification reuse are described. In an embodiment, a system comprising a hardware processor core to execute instructions storage for a resource monitoring identification (RMID) recycling instructions to be executed by a hardware processor core, a logical processor to execute on the hardware processor core, the logical processor including associated storage for a RMID and state, are described.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Matthew Fleming, Edwin Verplanke, Andrew Herdrich, Ravishankar Iyer
  • Publication number: 20170351534
    Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
    Type: Application
    Filed: June 22, 2017
    Publication date: December 7, 2017
    Inventors: Andrew Herdrich, Ramesh Illikkal, Donald Newell, Ravishankar Iyer, Vineet Chadha
  • Publication number: 20170330040
    Abstract: System, apparatus, method, and computer readable media for on-the-fly captured video summarization. A video stream is incrementally summarized in concurrence with generation of the stream by a camera module. Saliency of the video stream summary is maintained as the stream evolves by updating the summary to include only the most significant frames. In one exemplary embodiment, saliency is determined by optimizing an objective function including terms that are indicative of both the diversity of a selection, and how representative the selection is to the processed portion of the video data corpus. A device platform including a CM and comporting with the exemplary architecture may provide video camera functionality at ultra-low power, and/or with ultra-low storage resources, and/or with ultra-low communication channel bandwidth.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 16, 2017
    Inventors: Shayok Chakraborty, Omesh Tickoo, Ravishankar Iyer
  • Publication number: 20170286777
    Abstract: System, apparatus, method, and computer readable media for on-the-fly captured video summarization. A video stream is incrementally summarized in concurrence with generation of the stream by a camera module. Saliency of the video stream summary is maintained as the stream evolves by updating the summary to include only the most significant frames. In one exemplary embodiment, saliency is determined by optimizing an objective function including terms that are indicative of both the diversity of a selection, and how representative the selection is to the processed portion of the video data corpus. A device platform including a CM and comporting with the exemplary architecture may provide video camera functionality at ultra-low power, and/or with ultra-low storage resources, and/or with ultra-low communication channel bandwidth.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 5, 2017
    Inventors: Shayok CHAKRABORTY, Omesh TICKOO, Ravishankar IYER
  • Publication number: 20170269906
    Abstract: Apparatuses, methods and storage medium associated with a model compute system for physical programming are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify first rules associated with one or more physical subcomponents, e.g., blocks, tiles, or the like, or combinations thereof, assembled in a constructed model in a first control modality, wherein at least one first rule defines a first predetermined behavior of the constructed model, and determine a first program stack for execution by the model compute system based on the first rules associated with the one or more physical subcomponents. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 15, 2016
    Publication date: September 21, 2017
    Inventors: GLEN J. ANDERSON, REBECCA A. CHIERICHETTI, MENG SHI, YEVGENIY Y. YARMOSH, MARK R. FRANCIS, RAVISHANKAR IYER, REESE BOWES, ANKUR AGRAWAL
  • Patent number: 9769050
    Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance control. In various embodiments, an apparatus for computing may receive a datacenter performance target, determine an end-to-end datacenter performance level based at least in part on quality of service data collected from a plurality of nodes, and send a mitigation command based at least in part on a result of a comparison of the end-to-end datacenter performance level determined to the datacenter performance target. In various embodiments, the apparatus for computing may include one or more processors, a memory, a datacenter performance monitor to receive a datacenter performance target corresponding to a service level agreement, and a mitigation module to send a mitigation command based at least in part on a result of a comparison of an end-to-end datacenter performance level to a datacenter performance target.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Andrew J. Herdrich, Patrick Connor, Dinesh Kumar, Alexander W. Min, Ravishankar Iyer, Daniel J. Dahle, Kapil Sood, Jeffrey B. Shaw
  • Patent number: 9760794
    Abstract: Techniques for a system, article, and method of low-complexity histogram of gradients generation for image processing may include histogram of gradients generation for image processing including the following operations: obtaining image data including horizontal and vertical gradient components of individual pixels of an image; associating the horizontal and vertical gradient components of the same pixel with one of a plurality of angular channels depending on the values of the horizontal and vertical gradient components; determining a gradient magnitude and a gradient orientation of individual angular channels after the horizontal and vertical gradient components are assigned to the channels; and generating a histogram of gradients by using the gradient direction and gradient magnitude of the angular channels.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Teahyung Lee, Myung Hwangbo, Tanfer Alan, Omesh Tickoo, Ravishankar Iyer
  • Patent number: 9755997
    Abstract: Methods and apparatus for efficient peer-to-peer communication support in interconnect fabrics. Network interfaces associated with agents are implemented to facilitate peer-to-peer transactions between agents in a manner that ensures data accesses correspond to the most recent update for each agent. This is implemented, in part, via use of non-posted “dummy writes” that are sent from an agent when the destination between write transactions originating from the agent changes. The dummy writes ensure that data corresponding to previous writes reach their destination prior to subsequent write and read transactions, thus ordering the peer-to-peer transactions without requiring the use of a centralized transaction ordering entity.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Bin Li, Li Zhao, Ravishankar Iyer, Rameshkumar G. Illikkal
  • Patent number: 9751138
    Abstract: A composite milling cutter includes a rotatable adapter plate and ring cutter. The adapter plate has a raised key portion with a peripheral side wall having a plurality of curved abutment surfaces symmetrically located on an inscribed circle, ICAP defined by the raised key portion. The cutter ring has an opening with a peripheral side wall for receiving the raised key portion of the adapter plate. The peripheral side wall has a plurality of curved abutment surfaces complimentary in shape to the curved abutment surfaces of the adapter plate and symmetrically located on an inscribed circle, ICCR, defined by the opening. A tolerance between the abutment surfaces of the peripheral side wall of the raised key portion and the abutment surfaces of the peripheral wall of the opening is such that run-out is minimized.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: September 5, 2017
    Assignee: KENNAMETAL INC.
    Inventors: Lewis Ray Morrison, Ravishankar Iyer, Mark A. Kerin
  • Patent number: 9733987
    Abstract: Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of configurable computing resources based on relative priority among the virtual element and service chains. Information including indications of the performance of the service chains and also the relative priority of the service chains may be received. The resource allocation of portions of the shared pool of configurable computing resources supporting the service chains can be adjusted based on the received performance and priority information.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: August 15, 2017
    Assignee: INTEL CORPORATION
    Inventors: Andrew J. Herdrich, Kapil Sood, Nrupal R. Jani, David J. Harriman, Mesut A. Ergin, Scott P. Dubal, Ravishankar Iyer
  • Patent number: 9715397
    Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: July 25, 2017
    Assignee: Intel Corporation
    Inventors: Andrew Herdrich, Ramesh Illikkal, Donald Newell, Ravishankar Iyer, Vineet Chadha
  • Publication number: 20170192887
    Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 6, 2017
    Inventors: Andrew J. Herdrich, Edwin Verplanke, Ravishankar Iyer, Christopher C. Gianos, Jeffrey D. Chamberlain, Ronak Singhal, Julius Mandelblat, Bret L. Toll
  • Patent number: 9692756
    Abstract: Methods, apparatuses, systems, and storage media for creating, discovering, and/or resolving spells using a wand are provided. In embodiments, a computing device or a wand may detect one or more gestures and sensors in the wand may generate sensor data representative of the one or more gestures. The one or more gestures may be movements performed using the wand. The sensor data representative of the one or more gestures may be converted into a spell sequence. The wand may transmit the spell sequence to a computing device, and receive, from the computing device, an authentication spell output when the spell sequence corresponds with an authentication spell sequence or an inactivation spell output when the spell sequence does not correspond with the authentication spell sequence. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 27, 2017
    Assignee: INTEL CORPORATION
    Inventors: David I. Poisner, Gregory A. Peek, Blanka Vlasak, Yevgeniy Y. Yarmosh, Mark R. Francis, Ravishankar Iyer
  • Publication number: 20170173455
    Abstract: Systems, apparatuses and methods may provide for determining a state of a multi-player game and identifying a user communication associated with the multi-player game. Additionally, an outbound communication may be generated based on the user communication and the state of the multi-player game. In one example, generating the outbound communication includes conducting a weighted selection of one or more of a recipient, a content or an audio effect of the outbound communication based on the state.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Daniel P. Sheil, Glen J. Anderson, Mark R. Francis, Ravishankar Iyer, Yevgeniy Y. Yarmosh
  • Patent number: 9653070
    Abstract: A disclosed speech processor includes a front end to receive a speech input and generate a feature vector indicative of a portion of the speech input and a Gaussian mixture (GMM) circuit to receive the feature vector, model any one of a plurality of GMM speech recognition algorithms, and generate a GMM score for the feature vector based on the GMM speech recognition algorithm modeled. In at least one embodiment, the GMM circuit includes a common compute block to generate feature a vector sum indicative of a weighted sum of differences squares between the feature vector and a mixture component of the GMM speech recognition algorithm. In at least one embodiment, the GMM speech recognition algorithm being modeled includes a plurality of Gaussian mixture components and the common compute block is operable to generate feature vector scores corresponding to each of the plurality of mixture components.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Jenny Chang, Michael E. Deisher, Ravishankar Iyer
  • Patent number: 9639372
    Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 2, 2017
    Assignee: INTEL CORPORATION
    Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
  • Patent number: 9639762
    Abstract: System, apparatus, method, and computer readable media for on-the-fly captured video summarization. A video stream is incrementally summarized in concurrence with generation of the stream by a camera module. Saliency of the video stream summary is maintained as the stream evolves by updating the summary to include only the most significant frames. In one exemplary embodiment, saliency is determined by optimizing an objective function including terms that are indicative of both the diversity of a selection, and how representative the selection is to the processed portion of the video data corpus. A device platform including a CM and comporting with the exemplary architecture may provide video camera functionality at ultra-low power, and/or with ultra-low storage resources, and/or with ultra-low communication channel bandwidth.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Shayok Chakraborty, Omesh Tickoo, Ravishankar Iyer
  • Patent number: 9626586
    Abstract: Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Yong Zhang, Ravishankar Iyer, Rameshkumar G. Illikkal, Donald K. Newell, Jianping Zhou
  • Publication number: 20170091346
    Abstract: Technologies for physical programming include a model compute system to determine one or more physical blocks assembled in a constructed model. The model compute system determines rules associated with the one or more physical blocks in which at least one rule defines a behavior of the constructed model and determines a program stack for execution by the model compute system based on the rules associated with the one or more physical blocks.
    Type: Application
    Filed: September 26, 2015
    Publication date: March 30, 2017
    Inventors: Glen J. Anderson, Kevin W. Bross, Shawn S. Mceuen, Mark R. Francis, Yevgeniy Y. Yarmosh, Blanka Vlasak, Gregory A. Peek, Therese E. Dugan, Cory A. Harris, Ravishankar Iyer, Omesh Tickoo, David I. Poisner
  • Publication number: 20170092994
    Abstract: A battery includes integrated circuitry. The battery may include, for example, a substrate with a battery cell including an anode and a cathode. One or more electrical devices may be integrated on or within the substrate and configured to receive power from the anode and cathode. A package containing the substrate and the one or more electrical devices may include a first battery terminal electrically coupled to the anode and a second battery terminal electrically coupled to the cathode. The one or more electrical devices may include sensing circuitry to generate sensor data, and communication circuitry to provide the sensor data external to the package.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Applicant: INTEL CORPORATION
    Inventors: Dwayne E. Canfield, Ravishankar Iyer, Andrew W. Keates, Gregory A. Peek, Mark C. Pontarelli