Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance control. In various embodiments, an apparatus for computing may receive a datacenter performance target, determine an end-to-end datacenter performance level based at least in part on quality of service data collected from a plurality of nodes, and send a mitigation command based at least in part on a result of a comparison of the end-to-end datacenter performance level determined to the datacenter performance target. In various embodiments, the apparatus for computing may include one or more processors, a memory, a datacenter performance monitor to receive a datacenter performance target corresponding to a service level agreement, and a mitigation module to send a mitigation command based at least in part on a result of a comparison of an end-to-end datacenter performance level to a datacenter performance target.

Abstract: Apparatuses, methods and storage media for providing augmented reality (AR) effects in stop-motion content are described. In one instance, an apparatus may include a processor, a content module to be operated by the processor to obtain a plurality of frames having stop-motion content, some of which may include an indication of an augmented reality effect, and an augmentation module to be operated by the processor to detect the indication of the augmented reality effect and add the augmented reality effect corresponding to the indication to some of the plurality of frames. Other embodiments may be described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.

Abstract: A heterogeneous processor architecture is described.

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract: System, apparatus, method, and computer readable media for on-the-fly captured video summarization. A video stream is incrementally summarized in concurrence with generation of the stream by a camera module. Saliency of the video stream summary is maintained as the stream evolves by updating the summary to include only the most significant frames. In one exemplary embodiment, saliency is determined by optimizing an objective function including terms that are indicative of both the diversity of a selection, and how representative the selection is to the processed portion of the video data corpus. A device platform including a CM and comporting with the exemplary architecture may provide video camera functionality at ultra-low power, and/or with ultra-low storage resources, and/or with ultra-low communication channel bandwidth.

Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.

Abstract: A cutting tool includes a cutter body and a shower cap removably secured to the cutter body. The shower cap includes a cylindrical inside reservoir surface, a cylindrical outside coolant passage surface spaced radially outward from the cylindrical inside reservoir surface, and at least one coolant passage extending radially outward from the cylindrical inside reservoir surface to the cylindrical outside coolant passage surface. The at least one coolant passage is in fluid communication with an inlet opening formed in the cylindrical inside reservoir surface and an outlet opening formed in the cylindrical outside coolant passage surface such that coolant is directed radially outward from the cylindrical inside reservoir surface through the at least one coolant passage to a vicinity of a cutting insert within an insert-receiving pocket of the cutter body.

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract: A double-sided, nonagon cutting insert includes a top surface, a bottom surface identical to the top surface, nine side surfaces that are identical to each other, a cutting edge formed at an intersection between each of the nine side surfaces and the top and bottom surfaces for a total of eighteen cutting edges, and nine corner radiuses identical to each other, each corner radius extending between the top and bottom surfaces and each of the nine side surfaces. Each cutting edge has a non-symmetric profile with respect to a central, longitudinal axis. The non-symmetrical profile of the cutting edge has the technical advantage of providing a variable cutting force, particularly during fine finishing cutting operations.

Abstract: A screw head wedge clamp assembly for a cutting tool includes a clamp screw having a screw head with a frustum-shaped portion, and a screw head wedge clamp having a body and a clamp head extending from the body. The clamp head has a frustum-shaped portion that is received in a mounting screw bore of a cutting insert. The wedge clamp contacts a radiused bottom wall of the clamp bore when the clamp screw is threaded into a threaded bore of an insert pocket, thereby causing the clamp head to exert a downward and rearward force against a mounting screw bore of the cutting insert to securely hold the cutting insert in the insert pocket. The screw head wedge clamp does not contact a top surface of the cutting insert, but only the frustum-shaped portion contacts the mounting screw bore of the cutting insert.

Abstract: An indexable cutting insert includes a top surface, a bottom surface and a plurality of side surfaces. Each side surface includes a first pair of chip grooves, and a second pair of chip grooves. A planar corner surface is disposed between each side surface. A corner radius extends between the top and bottom surfaces and the planar corner surface. A plurality of primary wiper cutting edges are formed at an intersection between each of the first pair of chip grooves and the top and bottom surfaces. A plurality of secondary roughing cutting edges are formed at an intersection between each corner radius and each of the first pair of chip forming grooves. A plurality of wiper cutting edges are formed at an intersection between each planar corner surface and each of the second pair of chip forming grooves. A milling cutter is also disclosed.

Abstract: Systems and methods may provide for capturing a user input by emulating a touch screen mechanism. In one example, the method may include identifying a point of interest on a front facing display of the device based on gaze information associated with a user of the device, identifying a hand action based on gesture information associated with the user of the device, and initiating a device action with respect to the front facing display based on the point of interest and the hand action.

Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.

Abstract: A cutting tool (has a central, longitudinal axis and a tool body including an insert pocket with a bottom wall, a rear wall and at least one side wall. A cantilevered member is machined from the tool body so as to be integrally formed with the tool body. The cantilevered member extends from one of the walls of the insert pocket. An adjustment screw exerts a force against the cantilevered member to selectively adjust a position of a cutting insert mounted on the cantilevered member with respect to the central, longitudinal axis of the cutting tool. A method for selectively adjusting a position of the cutting insert is also disclosed.

Abstract: Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions.

Abstract: A double-sided, nonagon cutting insert includes a top surface, a bottom surface identical to the top surface, nine side surfaces that are identical to each other, a cutting edge formed at an intersection between each of the nine side surfaces and the top and bottom surfaces for a total of eighteen cutting edges, and nine corner radiuses identical to each other, each corner radius extending between the top and bottom surfaces and each of the nine side surfaces. Each cutting edge has a non-symmetric profile with respect to a central, longitudinal axis. The non-symmetrical profile of the cutting edge has the technical advantage of providing a variable cutting force, particularly during fine finishing cutting operations.