Patents by Inventor Ravishankar Iyer

Ravishankar Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170080332
    Abstract: Methods, apparatuses, systems, and storage media for creating, discovering, and/or resolving spells using a wand are provided. In embodiments, a computing device or a wand may detect one or more gestures and sensors in the wand may generate sensor data representative of the one or more gestures. The one or more gestures may be movements performed using the wand. The sensor data representative of the one or more gestures may be converted into a spell sequence. The wand may transmit the spell sequence to a computing device, and receive, from the computing device, an acknowledgement that is to indicate whether the wand is to be included in a duel with another wand based on the spell sequence and a wand position. The wand may also determine the spell output based on the spell sequence without transmitting the spell sequence to another device. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: DAVID I. POISNER, GREGORY A. PEEK, BLANKA VLASAK, YEVGENIY Y. YARMOSH, MARK R. FRANCIS, RAVISHANKAR IYER
  • Patent number: 9603079
    Abstract: A route for establishing a wireless connection between a wireless device and a node may be selected based on an estimated duration of the route. The route duration may be estimated based on information related to the expected movement of nodes included in the route.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Omesh Tickoo, Ravishankar Iyer
  • Patent number: 9584950
    Abstract: A social network may be established between mobile nodes using a wireless connection. Establishing the social network may be based on an estimated time duration of the wireless connection. In one or more embodiments, establishing the social network may also be based on a similarity of interests among of users of the nodes.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Omesh Tickoo, Ravishankar Iyer
  • Patent number: 9563579
    Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Daniel F. Cutter, Blaise Fanning, Ramadass Nagarajan, Ravishankar Iyer, Quang T. Le, Ravi Kolagotla, Ioannis T. Schoinas, Jose S. Niell
  • Patent number: 9563564
    Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Andrew J. Herdrich, Edwin Verplanke, Ravishankar Iyer, Christopher C. Gianos, Jeffrey D. Chamberlain, Ronak Singhal, Julius Mandelblat, Bret L. Toll
  • Patent number: 9535860
    Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Daniel F. Cutter, Blaise Fanning, Ramadass Nagarajan, Jose S. Niell, Debra Bernstein, Deepak Limaye, Ioannis T. Schoinas, Ravishankar Iyer
  • Publication number: 20160375372
    Abstract: Apparatuses and methods associated with block structure and robot cooperation are disclosed herein. In embodiments, a block apparatus may include a block structure-robot coordination module to cooperate with one or more robots to affect operations of the one or more robots relative to at least a block structure which the block apparatus is a member. The block apparatus may further include a housing that houses the block structure-robot coordination module, with features to mate the block apparatus with one or more other blocks to cause the block apparatus to become a member of the block structure. In embodiments, a robot may include control module to control a number of actuators to operate one or more features to perform one or more operations relative to the block structure. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Inventors: Glen J. Anderson, Yevgeniy Y. Yarmosh, David I. Poisner, Gregory A. Peek, Mark R. Francis, Ravishankar Iyer
  • Publication number: 20160379684
    Abstract: Examples include a determination how to manage storage of a video clip generated from recorded video based upon a sensor event. Managing storage of the video clip may include determining whether to save or delete the video clip based on an imprint associated with an object that indicates whether the object is included in the video clip.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Applicant: Intel Corporation
    Inventors: Glen J. ANDERSON, Kathy YUEN, Joshua EKANDEM, Omesh TICKOO, Ravishankar IYER
  • Publication number: 20160375354
    Abstract: A mechanism is described for facilitating dynamic game surface adjustment at smart play surfaces of smart play sets according to one embodiment. A method of embodiments, as described herein, includes receiving one or more inputs to perform an action at a portion of a play surface of a play set; evaluating the one or more inputs for generating an action plan to perform the action at the portion of the play surface, where the action plan is to affect one or more objects acting on the surface. The method may further include executing the action at the portion of the surface, wherein the action to adjust one or more properties of the play surface.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: MARK R. FRANCIS, OMESH TICKOO, RAVISHANKAR IYER, GLEN J. ANDERSON, KEVIN W. BROSS, DAVID I. POISNER, YEVGENIY Y. YARMOSH, DANIEL P. SHEIL
  • Publication number: 20160381171
    Abstract: A mechanism is described for dynamically facilitating media play and real-time interaction with smart physical objects according to one embodiment. A method of embodiments, as described herein, includes seeking one or more personal devices accessible to one or more users; presenting media contents; detecting, in real-time, an update relating to the media contents; recommending one or more revisions to activities or arrangements relating to the one or more personal devices based on the update relating to the media contents; preparing a set of instructions detailing the one or more revisions to the activities or the arrangements; and executing the set of instructions to facilitate the one or more revisions to the activities or the arrangements relating to the one or more personal devices.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: GLEN J. ANDERSON, MARK R. FRANCIS, RAVISHANKAR IYER, YEVGENIY Y. YARMOSH, KEVIN W. BROSS
  • Patent number: 9475138
    Abstract: A cutting tool (has a central, longitudinal axis and a tool body including an insert pocket with a bottom wall, a rear wall and at least one side wall. A cantilevered member is machined from the tool body so as to be integrally formed with the tool body. The cantilevered member extends from one of the walls of the insert pocket. An adjustment screw exerts a force against the cantilevered member to selectively adjust a position of a cutting insert mounted on the cantilevered member with respect to the central, longitudinal axis of the cutting tool. A method for selectively adjusting a position of the cutting insert is also disclosed.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: October 25, 2016
    Assignee: KENNAMETAL INC.
    Inventors: Lewis Ray Morrison, Ravishankar Iyer, Scott Patrick Rusnock
  • Publication number: 20160306630
    Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventors: ZHEN FANG, XIAOWEI JIANG, SRIHARI MAKINENI, RAMESHKUMAR G. ILLIKKAL, RAVISHANKAR IYER
  • Publication number: 20160306415
    Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadagopan Srinivasan, Jaideep Moses, Srihari Makineni
  • Publication number: 20160299849
    Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.
    Type: Application
    Filed: April 7, 2015
    Publication date: October 13, 2016
    Inventors: ANDREW J. HERDRICH, EDWIN VERPLANKE, RAVISHANKAR IYER, CHRISTOPHER C. GIANOS, JEFFREY D. CHAMBERLAIN, RONAK SINGHAL, JULIUS MANDELBLAT, BRET L. TOLL
  • Publication number: 20160299559
    Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 13, 2016
    Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadogopan Srinivasan, Jaideep Moses, Srihari Makineni
  • Publication number: 20160299558
    Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 13, 2016
    Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadogopan Srinivasan, Jaideep Moses, Srihari Makineni
  • Patent number: 9465751
    Abstract: An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: October 11, 2016
    Assignee: Intel Corporation
    Inventors: Xiaowei Jiang, Hongliang Gao, Zhen Fang, Srihari Makineni, Ravishankar Iyer
  • Publication number: 20160284021
    Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Andrew HERDRICH, Edwin VERPLANKE, Ravishankar IYER, Christopher GIANOS, Jeffrey D. CHAMBERLAIN, Ronak SINGH, Julius MANDELBLAT, Bret Toll
  • Publication number: 20160250696
    Abstract: A composite milling cutter includes a rotatable adapter plate and ring cutter. The adapter plate has a raised key portion with a peripheral side wall having a plurality of curved abutment surfaces symmetrically located on an inscribed circle, ICAP defined by the raised key portion. The cutter ring has an opening with a peripheral side wall for receiving the raised key portion of the adapter plate. The peripheral side wall has a plurality of curved abutment surfaces complimentary in shape to the curved abutment surfaces of the adapter plate and symmetrically located on an inscribed circle, ICCR, defined by the opening. A tolerance between the abutment surfaces of the peripheral side wall of the raised key portion and the abutment surfaces of the peripheral wall of the opening is such that run-out is minimized.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: Lewis Ray Morrison, Ravishankar Iyer, Mark A. Kerin
  • Publication number: 20160246652
    Abstract: Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of configurable computing resources based on relative priority among the virtual element and service chains. Information including indications of the performance of the service chains and also the relative priority of the service chains may be received. The resource allocation of portions of the shared pool of configurable computing resources supporting the service chains can be adjusted based on the received performance and priority information.
    Type: Application
    Filed: February 20, 2015
    Publication date: August 25, 2016
    Inventors: ANDREW J. HERDRICH, KAPIL SOOD, NRUPAL R. JANI, DAVID J. HARRIMAN, MESUT A. ERGIN, SCOTT P. DUBAL, RAVISHANKAR IYER