Abstract: A method is provided for making an interconnect structure. The method includes applying a low-temperature removable layer and adhesive layer to an electronic device or to a base insulative layer; and securing the electronic device to the base insulative layer using the adhesive layer.

Abstract: A method for making an interconnect structure includes applying a first metal layer to an electronic device, wherein the electronic device comprises at least one I/O contact and the first metal layer is located on a surface of the I/O contact; applying a removable layer to the electronic device. The removable layer is adjacent to the first metal layer. An adhesive layer is applied to the electronic device or to a base insulative layer. The electronic device is secured to the base insulative layer using the adhesive layer. The first metal layer and removable layer are disposed between the electronic device and the base insulative layer.

Abstract: An electronic component includes a base insulative layer having a first surface and a second surface; an electronic device having a first surface and a second surface, and the electronic device being secured to the base insulative layer; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer. The base insulative layer secures to the electronic device through the removable layer. The removable layer is capable of releasing the base insulative layer from the electronic device. The removal may be done without damage to a predetermined part of the electronic component.

Abstract: A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.

Abstract: A FET includes elongated, mutually parallel source regions separated by gate and drain regions. Conductive bridges extend over the gate and drain regions and not in electrical contact therewith to electrically and thermally interconnect the sources. A layer of dielectric is applied over surfaces, and an aperture is defined over the bridges. A thick layer of metal is applied over and in thermal and electrical contact with the bridges. Electrical and thermal connections can be made to the thick metal.

Abstract: A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

Abstract: An interconnection structure includes: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optional additional portion of cured adhesive, the additional portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.

Abstract: An interconnection structure includes: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optional additional portion of cured adhesive, the additional portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.

Abstract: An interconnection structure includes: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optional additional portion of cured adhesive, the additional portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.

Abstract: One type of electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island. Another type of electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.

Abstract: One type of electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island. Another type of electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.

Abstract: An interconnection structure includes: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optional additional portion of cured adhesive, the additional portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.

Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.

Abstract: A power semiconductor device package includes at least one power semiconductor device mounted onto at least one electrically and thermally conductive spacer having an upper end surface bonded to a back surface of the device; a substrate of hardened substrate molding material surrounding the semiconductor device and the spacer except for an active major surface of the device and an lower end surface of the spacer, a dielectric film overlying the device active major surface and a top side of the substrate, the dielectric layer having a plurality of holes aligned with predetermined ones of the contact pads; a top side patterned metal layer on the dielectric film including portions extending into the holes electrically and thermally connected to contact pads of the device; and a backside metal layer on a substrate bottom side electrically and thermally connected to the spacer lower end surface.

Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.

Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.

Abstract: An integrated circuit package includes at least one integrated circuit element coupled to a polymer film; a window frame coupled to the polymer film and surrounding the at least one integrated circuit element; and encapsulant material positioned between the at least one integrated circuit element and the window frame.

Abstract: A circuit design is logically partitioned into a plurality of blocks. As a first hierarchial assembly level, the blocks are fabricated as individual submodules each including at least one electronic component with component connection pads on a top surface, and a first interconnect structure including at least one interconnect layer bonded to the top surfaces, and interconnecting selected ones of the component connection pads. Submodule connection pads are provided on upper surfaces of the submodules. As a second hierarchial assembly level, a second interconnect structure is bonded to the upper surfaces and interconnects selected ones of the submodule connection pads.

Abstract: A burn-in frame having at least one window and including resistors having resistor pads is situated on a flexible layer, and at least one integrated circuit chip having chip pads is situated in the at least one window. Via openings are formed in the flexible layer to extend to the chip pads and the resistor pads. A pattern of electrical conductors is applied over the flexible layer and extending into the vias. The at least one integrated circuit chip is burned in. The burn-in frame may further include fuses, frame contacts, and voltage bias tracks. After burning in the at least one integrated circuit chip, the chip pads can be electrically isolated and the at least one integrated circuit chip can be tested. This method can also be used to burn-in and test multichip modules.

Abstract: A burn-in frame having at least one window and including resistors having resistor pads is situated on a flexible layer, and at least one integrated circuit chip having chip pads is situated in the at least one window. Via openings are formed in the flexible layer to extend to the chip pads and the resistor pads. A pattern of electrical conductors is applied over the flexible layer and extending into the vias. The at least one integrated circuit chip is burned in. The burn-in frame may further include fuses, frame contacts, and voltage bias tracks. After burning in the at least one integrated circuit chip, the chip pads can be electrically isolated and the at least one integrated circuit chip can be tested. This method can also be used to burn-in and test multichip modules.