Patents by Inventor Raymond J. Beffa
Raymond J. Beffa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8189423Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip.Type: GrantFiled: June 24, 2011Date of Patent: May 29, 2012Assignee: Round Rock Research, LLCInventors: Brent Keeth, Layne G. Bunker, Raymond J. Beffa, Frank F. Ross
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Publication number: 20110261628Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: June 24, 2011Publication date: October 27, 2011Applicant: Round Rock Research, LLCInventors: Brent Keeth, Layne G. Bunker, Scott J. Demer, Ronald L. Taylor, John S. Mullin, Raymond J. Beffa, Frank F. Ross, Larry D. Kinsman
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Patent number: 7969810Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: March 6, 2009Date of Patent: June 28, 2011Assignee: Round Rock Research, LLCInventors: Brent Keeth, Layne G. Bunker, Scott J. Demer, Ronald L Taylor, John S. Mullin, Raymond J. Beffa, Frank F. Ross, Larry D. Kinsman
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Publication number: 20110089088Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.Type: ApplicationFiled: December 28, 2010Publication date: April 21, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Raymond J. Beffa
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Patent number: 7885782Abstract: A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad ICs on the wafer and the fuse IDs of the ICs on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC in each device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad ICs that have accidentally been assembled into IC devices. Any “bad” IC devices are discarded while remaining IC devices continue on to back-end testing.Type: GrantFiled: October 17, 2006Date of Patent: February 8, 2011Assignee: Micron Technology, Inc.Inventor: Raymond J. Beffa
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Patent number: 7875821Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.Type: GrantFiled: October 9, 2008Date of Patent: January 25, 2011Assignee: Micron Technology, Inc.Inventor: Raymond J. Beffa
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Patent number: 7682847Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.Type: GrantFiled: October 9, 2008Date of Patent: March 23, 2010Assignee: Micron Technology, Inc.Inventor: Raymond J. Beffa
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Publication number: 20090273360Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: ApplicationFiled: July 16, 2009Publication date: November 5, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud
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Publication number: 20090245009Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: ApplicationFiled: March 6, 2009Publication date: October 1, 2009Inventors: Brent Keeth, Layne G. Bunker, Scott J. Demer, Ronald L. Taylor, John S. Mullin, Raymond J. Beffa, Frank F. Ross, Larry D. Kinsman
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Patent number: 7567091Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: GrantFiled: January 21, 2008Date of Patent: July 28, 2009Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud
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Patent number: 7502659Abstract: A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with the fuse ID of each of the devices indicating each of the devices requires either enhanced reliability testing or standard testing. The fuse ID of each of the devices is then automatically read before, during, or after standard testing of the devices. The testing process requirement data stored in association with the fuse ID of each of the devices is then accessed, and the devices are sorted in accordance with the accessed data into those devices requiring enhanced reliability testing and those requiring standard testing.Type: GrantFiled: October 3, 2006Date of Patent: March 10, 2009Assignee: Micron Technology, Inc.Inventor: Raymond J. Beffa
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Publication number: 20090060703Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.Type: ApplicationFiled: October 9, 2008Publication date: March 5, 2009Applicant: MICRON TECHNOLOGY, INC.Inventor: Raymond J. Beffa
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Publication number: 20090038997Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.Type: ApplicationFiled: October 9, 2008Publication date: February 12, 2009Applicant: Micron Technology, Inc.Inventor: Raymond J. Beffa
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Patent number: 7489564Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: June 14, 2006Date of Patent: February 10, 2009Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Raymond J. Beffa, Frank F. Ross
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Patent number: 7477557Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip.Type: GrantFiled: June 14, 2006Date of Patent: January 13, 2009Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Raymond J. Beffa, Frank F. Ross
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Patent number: 7477556Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.Type: GrantFiled: July 6, 2001Date of Patent: January 13, 2009Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Layne G. Bunker, Raymond J. Beffa, Frank F. Ross
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Patent number: 7446277Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.Type: GrantFiled: March 6, 2002Date of Patent: November 4, 2008Assignee: Micron Technology, Inc.Inventor: Raymond J. Beffa
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Patent number: 7368678Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.Type: GrantFiled: August 13, 2002Date of Patent: May 6, 2008Assignee: Micron Technology, Inc.Inventor: Raymond J. Beffa
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Patent number: 7323896Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: GrantFiled: December 1, 2006Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud
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Patent number: 7315179Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.Type: GrantFiled: December 1, 2006Date of Patent: January 1, 2008Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud