Patents by Inventor Reika Ichihara

Reika Ichihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446227
    Abstract: According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kensuke Ota, Masamichi Suzuki, Reika Ichihara
  • Patent number: 10446552
    Abstract: According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer includes an ion source. The first layer includes a first element and is provided between the first conductive layer and the second conductive layer. An electronegativity of the first element is greater than 2. The first layer includes a first region and a second region. The first region includes the first element. The second region is provided between the first region and the second conductive layer. The second region does not include the first element, or the second region includes the first element, and a concentration of the first element in the first region is higher than a concentration of the first element in the second region.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Dandan Zhao, Reika Ichihara, Haruka Sakuma, Yuuichiro Mitani
  • Publication number: 20190088324
    Abstract: According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.
    Type: Application
    Filed: March 5, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Kensuke OTA, Masamichi Suzuki, Reika Ichihara
  • Publication number: 20190088655
    Abstract: According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer includes an ion source. The first layer includes a first element and is provided between the first conductive layer and the second conductive layer. An electronegativity of the first element is greater than 2. The first layer includes a first region and a second region. The first region includes the first element. The second region is provided between the first region and the second conductive layer. The second region does not include the first element, or the second region includes the first element, and a concentration of the first element in the first region is higher than a concentration of the first element in the second region.
    Type: Application
    Filed: March 6, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Dandan ZHAO, Reika ICHIHARA, Haruka SAKUMA, Yuuichiro MITANI
  • Patent number: 9928908
    Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Reika Ichihara, Daisuke Matsushita, Shosuke Fujii
  • Patent number: 9779808
    Abstract: A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects and one of the first interconnects for a first time when switching resistance states of the variable resistance members from a first state to a second state, and the control circuit applies a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state. The second voltage has the same polarity as the first voltage and is lower than the first voltage. The second time is longer than the first time.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 3, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Arayashiki, Kikuko Sugimae, Reika Ichihara
  • Publication number: 20170256310
    Abstract: A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects and one of the first interconnects for a first time when switching resistance states of the variable resistance members from a first state to a second state, and the control circuit applies a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state. The second voltage has the same polarity as the first voltage and is lower than the first voltage. The second time is longer than the first time.
    Type: Application
    Filed: September 12, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke ARAYASHIKI, Kikuko SUGIMAE, Reika ICHIHARA
  • Patent number: 9691978
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first wirings, a plurality of second wirings, a variable resistance layer, a first barrier insulating layer, and a second barrier insulating layer. The first wirings are disposed at predetermined pitches in a first direction intersecting with a substrate. The second wirings are disposed at predetermined pitches in a second direction intersecting with the first direction. The second wirings are formed to extend in the first direction. The variable resistance layer is disposed between the first wiring and the second wiring. The variable resistance layer is disposed at a position where the first wiring intersects with the second wiring. The first barrier insulating layer is disposed between the first wiring and the variable resistance layer. The second barrier insulating layer is disposed between the second wiring and the variable resistance layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: June 27, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shuichi Toriyama, Reika Ichihara
  • Patent number: 9679644
    Abstract: A semiconductor storage device includes a variable resistive element, which changes a resistance value according to a polarity and a magnitude of an applied voltage, as a memory element. The semiconductor storage device includes a standby mode in which a power source voltage or a ground voltage is applied to both of a word line and a bit line. The semiconductor storage device includes a data write mode in which a voltage difference equal to or more than a first voltage is applied between the word line and the bit line. The semiconductor storage device includes a read mode in which a voltage difference smaller than the first voltage is applied between the word line and the bit line by changing only one voltage of the word line and the bit line which is applied in the standby mode, and data written in the memory element is read.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: June 13, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Miyazaki, Reika Ichihara, Kikuko Sugimae, Yoshihisa Iwata
  • Publication number: 20170148516
    Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Reika ICHIHARA, Daisuke MATSUSHITA, Shosuke FUJII
  • Publication number: 20170140818
    Abstract: A resistance variable memory has a controller configured to control a voltage to be applied to the memory cell. The controller has a reset operation to bring the memory cell into a reset state, a first operation to apply a set voltage between the first wire and the second wire, a second operation to determine whether a current flowing to the memory cell to be set exceeds a first threshold when a first reading voltage is applied between the first wire and the second wire, a third operation to determine whether a current flowing to the memory cell to be set exceeds a second threshold when a second reading voltage is applied between the first wire and the second wire, and a fourth operation to apply a second reset voltage, between the first wire and the second wire.
    Type: Application
    Filed: February 1, 2017
    Publication date: May 18, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kikuko SUGIMAE, Reika ICHIHARA
  • Patent number: 9607694
    Abstract: A semiconductor memory device according to the embodiments includes a first wiring, a second wiring that extends to intersect with the first wiring, a memory cell that is disposed on each intersection portion of the first wiring and the second wiring, and includes a variable resistive element, and a control circuit to control a voltage applied to the memory cell. The control circuit applies a read voltage with respect to the memory cell for a plurality of times to determine a resistive state of the memory cell for a plurality of times, so as to obtain a first determination result or a second determination result. The control circuit compares the number of the first determination result with the number of the second determination result, terminates a reading operation when the comparison result satisfies a certain condition, and starts the reading operation again when the condition is not satisfied.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: March 28, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Reika Ichihara
  • Publication number: 20170084330
    Abstract: A semiconductor memory device according to the embodiments includes a first wiring, a second wiring that extends to intersect with the first wiring, a memory cell that is disposed on each intersection portion of the first wiring and the second wiring, and includes a variable resistive element, and a control circuit to control a voltage applied to the memory cell. The control circuit applies a read voltage with respect to the memory cell for a plurality of times to determine a resistive state of the memory cell for a plurality of times, so as to obtain a first determination result or a second determination result. The control circuit compares the number of the first determination result with the number of the second determination result, terminates a reading operation when the comparison result satisfies a certain condition, and starts the reading operation again when the condition is not satisfied.
    Type: Application
    Filed: March 16, 2016
    Publication date: March 23, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Reika ICHIHARA
  • Patent number: 9601192
    Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: March 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Reika Ichihara, Daisuke Matsushita, Shosuke Fujii
  • Patent number: 9595327
    Abstract: A resistance variable memory has a controller configured to control a voltage to be applied to the memory cell. The controller has a reset operation to bring the memory cell into a reset state, a first operation to apply a set voltage between the first wire and the second wire, a second operation to determine whether a current flowing to the memory cell to be set exceeds a first threshold when a first reading voltage is applied between the first wire and the second wire, a third operation to determine whether a current flowing to the memory cell to be set exceeds a second threshold when a second reading voltage is applied between the first wire and the second wire, and a fourth operation to apply a second reset voltage, between the first wire and the second wire.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kikuko Sugimae, Reika Ichihara
  • Patent number: 9450065
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: September 20, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeki Hattori, Reika Ichihara, Masaya Terai, Hideyuki Nishizawa, Tsukasa Tada, Koji Asakawa, Hiroyuki Fuke, Satoshi Mikoshiba, Yoshiaki Fukuzumi, Hideaki Aochi
  • Publication number: 20160267974
    Abstract: A semiconductor storage device includes a variable resistive element, which changes a resistance value according to a polarity and a magnitude of an applied voltage, as a memory element. The semiconductor storage device includes a standby mode in which a power source voltage or a ground voltage is applied to both of a word line and a bit line. The semiconductor storage device includes a data write mode in which a voltage difference equal to or more than a first voltage is applied between the word line and the bit line. The semiconductor storage device includes a read mode in which a voltage difference smaller than the first voltage is applied between the word line and the bit line by changing only one voltage of the word line and the bit line which is applied in the standby mode, and data written in the memory element is read.
    Type: Application
    Filed: August 25, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takayuki MIYAZAKI, Reika ICHIHARA, Kikuko SUGIMAE, Yoshihisa IWATA
  • Publication number: 20160260482
    Abstract: A resistance variable memory has a controller configured to control a voltage to be applied to the memory cell. The controller has a reset operation to bring the memory cell into a reset state, a first operation to apply a set voltage between the first wire and the second wire, a second operation to determine whether a current flowing to the memory cell to be set exceeds a first threshold when a first reading voltage is applied between the first wire and the second wire, a third operation to determine whether a current flowing to the memory cell to be set exceeds a second threshold when a second reading voltage is applied between the first wire and the second wire, and a fourth operation to apply a second reset voltage, between the first wire and the second wire.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kikuko SUGIMAE, Reika Ichihara
  • Patent number: RE46271
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
  • Patent number: RE47640
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama