Abstract: A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit repeating: applying a first voltage for setting to the memory cell; and a verify read verifying that the resistance value of the memory cell has become lower than the predetermined resistance value. After the verify read, the control circuit applies a second voltage having a different polarity from the first voltage to the memory cell before applying the first voltage that follows.

Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a first layer and a second layer. The second electrode contains at least one metal element selected from Ag, Cu, Ni, Co, Al, and Ti. The first layer is arranged between the first electrode and the second electrode. The second layer is arranged between the first electrode and the first layer. A diffusion coefficient of the metal element in the second layer is larger than a diffusion coefficient of the metal element in the first layer.

Abstract: According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor, and a control circuit which is stored multi-level data to the memory cell by using the first and second voltage pulses in a writing.

Abstract: A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.

Abstract: A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.

Abstract: According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value, and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation. The stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers. Amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor. The first voltage pulse satisfies Ron×C<T-lead<Roff×C and Ron×C<T-trail.

Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.

Abstract: A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.

Abstract: Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.

Abstract: According to one embodiment, there are provided a first electrode, a second electrode containing a 1B group element having an Al element added thereto, and a variable resistive layer disposed between the first electrode and the second electrode and having a silicon element.

Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Abstract: According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value, and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation. The stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers. Amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor. The first voltage pulse satisfies Ron×C<T-lead<Roff×C and Ron×C<T-trail.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.

Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.

Abstract: A storage device includes: a plurality of first electrode wirings; a plurality of second electrode wirings which cross the first electrode wirings; a via plug which is formed between the second electrode wiring and the two adjacent first electrode wirings, and in which a maximum diameter of a bottom surface opposing the first electrode wirings in a direction vertical to a direction in which the first electrode wirings stretch is smaller than a length corresponding to a pitch of the first electrode wiring plus a width of the first electrode wirings; a first storage element which is formed between the via plug and one of the two first electrode wirings; and a second storage element which is formed between the via plug and the other one of the two first electrode wirings.

Abstract: A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.

Abstract: According to one embodiment, a first electrode includes a metal element. A second electrode includes a semiconductor element. A third electrode includes a metal element. A first variable resistive layer is arranged between the first electrode and the second electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the first electrode. A second variable resistive layer is arranged between the second electrode and the third electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the third electrode.

Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.