Patents by Inventor Reika Ichihara

Reika Ichihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150078064
    Abstract: A semiconductor memory device comprises: a plurality of first lines; a plurality of second lines extending to intersect the first lines; a plurality of memory cells disposed respectively at intersections of the first and second lines and including a variable resistance element; and a control circuit configured to control a voltage applied to the memory cell. The control circuit is configured able to, during a setting operation that changes the memory cell to a set state, execute the setting operation such that a setting voltage is applied to a selected memory cell connected to a selected first line and a selected second line. The control circuit is configured able to change a voltage application time of the setting voltage according to a state of change of the selected memory cell during the setting operation to execute an additional setting operation that applies the setting voltage to the selected memory cell.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chika TANAKA, Reika ICHIHARA, Yoshihisa IWATA
  • Patent number: 8975611
    Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamauchi, Shosuke Fujii, Reika Ichihara
  • Publication number: 20150044835
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.
    Type: Application
    Filed: September 25, 2014
    Publication date: February 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Hattori, Reika Ichihara, Masaya Terai, Hideyuki Nishizawa, Tsukasa Tada, Koji Asakawa, Hiroyuki Fuke, Satoshi Mikoshiba, Yoshiaki Fukuzumi, Hideaki Aochi
  • Publication number: 20140328110
    Abstract: A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit repeating: applying a first voltage for setting to the memory cell; and a verify read verifying that the resistance value of the memory cell has become lower than the predetermined resistance value. After the verify read, the control circuit applies a second voltage having a different polarity from the first voltage to the memory cell before applying the first voltage that follows.
    Type: Application
    Filed: July 17, 2014
    Publication date: November 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kikuko SUGIMAE, Reika Ichihara
  • Patent number: 8873275
    Abstract: According to one embodiment, a semiconductor storage device includes multiple memory cells that include a variable resistance element and a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured so that, during the set operation in which the variable resistance element is changed to the set state, a set voltage of a first polarity is applied to the select memory cell. The control circuit is configured so that, during the reset operation in which the variable resistance elements are changed to the reset state, and a cancel voltage of the first polarity is applied to an unselected memory cell to which voltage that is less than the reset voltage was applied. The voltage value and the voltage application time of the set voltage and the voltage value and the voltage application time of the cancel voltage have a set relationship.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Reika Ichihara
  • Publication number: 20140268999
    Abstract: According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.
    Type: Application
    Filed: September 3, 2013
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Reika ICHIHARA, Kikuko SUGIMAE, Takayuki MIYAZAKI, Yoshihisa IWATA
  • Publication number: 20140269000
    Abstract: According to one embodiment, a semiconductor storage device includes multiple memory cells that include a variable resistance element and a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured so that, during the set operation in which the variable resistance element is changed to the set state, a set voltage of a first polarity is applied to the select memory cell. The control circuit is configured so that, during the reset operation in which the variable resistance elements are changed to the reset state, and a cancel voltage of the first polarity is applied to an unselected memory cell to which voltage that is less than the reset voltage was applied. The voltage value and the voltage application time of the set voltage and the voltage value and the voltage application time of the cancel voltage have a set relationship.
    Type: Application
    Filed: September 3, 2013
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Reika ICHIHARA
  • Patent number: 8804401
    Abstract: A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit repeating: applying a first voltage for setting to the memory cell; and a verify read verifying that the resistance value of the memory cell has become lower than the predetermined resistance value. After the verify read, the control circuit applies a second voltage having a different polarity from the first voltage to the memory cell before applying the first voltage that follows.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kikuko Sugimae, Reika Ichihara
  • Publication number: 20140191184
    Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.
    Type: Application
    Filed: March 13, 2014
    Publication date: July 10, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi YAMAUCHI, Shosuke Fujii, Reika Ichihara
  • Patent number: 8759806
    Abstract: A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Yamaguchi, Hirofumi Inoue, Reika Ichihara, Takayuki Tsukamoto, Takashi Shigeoka, Katsuyuki Sekine, Shinya Aoki
  • Publication number: 20140138598
    Abstract: According to one embodiment, nonvolatile memory device includes a semiconductor layer, a conductive layer and a resistance change layer. The semiconductor layer has an impurity concentration less than 1×1019 cm?3. The resistance change layer is provided between the semiconductor layer and the conductive layer. The resistance change layer includes a fixed charge. The resistance change layer is reversibly transitionable between a first state and a second state by at least one selected from a current supplied via the semiconductor layer and the conductive layer and a voltage applied via the semiconductor layer and the conductive layer. A resistance of the resistance change layer in the second state is higher than a resistance of the resistance change layer in the first state.
    Type: Application
    Filed: September 13, 2013
    Publication date: May 22, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi Haimoto, Reika Ichihara, Yuuichiro Mitani, Masato Koyama
  • Publication number: 20140133210
    Abstract: An element according to an embodiment can transit between at least two states including a low-resistance state and a high-resistance state. The element comprises a first electrode, a second electrode, a first layer and a second layer. The first electrode includes metal elements. The first layer is located between the first electrode and the second electrode while contacting with the first electrode. The second layer is located between the first layer and the second electrode. At the low-resistance state, a density of the metal elements in the first layer is higher than that of the metal elements in the second layer. The density of the metal elements in the first layer at the low-resistance state is higher than that of the metal elements in the first layer at the high-resistance state. A relative permittivity of the second layer is higher than a relative permittivity of the first layer.
    Type: Application
    Filed: October 2, 2013
    Publication date: May 15, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Reika Ichihara, Daisuke Matsushita, Takayuki Ishikawa, Hiroki Tanaka
  • Patent number: 8698277
    Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamauchi, Shosuke Fujii, Reika Ichihara
  • Publication number: 20140097485
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.
    Type: Application
    Filed: December 13, 2013
    Publication date: April 10, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki HATTORI, Reika ICHIHARA, Masaya TERAI, Hideyuki NISHIZAWA, Tsukasa TADA, Koji ASAKAWA, Hiroyuki FUKE, Satoshi MIKOSHIBA, Yoshiaki FUKUZUMI, Hideaki AOCHI
  • Publication number: 20140092669
    Abstract: A non-volatile variable resistive element according to an embodiment comprises a first electrode including a first metal, a second electrode including a second metal, a third electrode placed opposite to the first and second electrodes, and a variable resistive layer placed between the first and second electrodes and the third electrode, a resistance of the variable resistive layer reducing when at least either one of the first metal and the second metal is diffused into the variable resistive layer and the resistance of the variable resistive layer rising when at least either one of the first metal and the second metal diffused into the variable resistive layer is collected by the first electrode or the second electrode.
    Type: Application
    Filed: August 13, 2013
    Publication date: April 3, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jiezhi CHEN, Reika Ichihara, Yuuichiro Mitani
  • Publication number: 20140071734
    Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell includes a first electrode, a second electrode, and a variable resistance layer which is disposed between the first electrode and the second electrode. The control circuit sets a current flowing through the memory cell to a first upper limit and applies a first voltage to the memory cell in a first write, and after the first write, the control circuit sets the current flowing through the memory cell to a second upper limit and applies a second voltage to the memory cell in a second write.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 13, 2014
    Inventors: Kikuko Sugimae, Reika Ichihara, Tetsuya Hayashi
  • Patent number: 8633526
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 21, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Hattori, Reika Ichihara, Masaya Terai, Hideyuki Nishizawa, Tsukasa Tada, Koji Asakawa, Hiroyuki Fuke, Satoshi Mikoshiba, Yoshiaki Fukuzumi, Hideaki Aochi
  • Publication number: 20140003130
    Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 2, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Reika ICHIHARA, Daisuke Matsushita, Shosuke Fujii
  • Patent number: 8610101
    Abstract: According to one embodiment, there are provided a first electrode, a second electrode containing a 1B group element having an Al element added thereto, and a variable resistive layer disposed between the first electrode and the second electrode and having a silicon element.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamauchi, Shosuke Fujii, Reika Ichihara
  • Patent number: 8575587
    Abstract: A storage device includes: a plurality of first electrode wirings; a plurality of second electrode wirings which cross the first electrode wirings; a via plug which is formed between the second electrode wiring and the two adjacent first electrode wirings, and in which a maximum diameter of a bottom surface opposing the first electrode wirings in a direction vertical to a direction in which the first electrode wirings stretch is smaller than a length corresponding to a pitch of the first electrode wiring plus a width of the first electrode wirings; a first storage element which is formed between the via plug and one of the two first electrode wirings; and a second storage element which is formed between the via plug and the other one of the two first electrode wirings.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Shigeki Hattori, Hideyuki Nishizawa, Satoshi Mikoshiba, Reika Ichihara, Masaya Terai