Abstract: Embodiments of present invention provide a biosensor structure. The biosensor structure includes a substrate having a frontside and a backside opposing the frontside; a sensing surface at the frontside of the substrate, the sensing surface being adapted to detect certain biomolecules in a test solution placed on the sensing surface; and a controlling surface at the backside of the substrate, the controlling surface providing access to a controlling terminal, and the controlling terminal being capacitively connected to the sensing surface. A method of forming the same is also provided.

Abstract: Embodiments of present invention provide a biosensor structure. The biosensor structure includes a sensing transistor having a source region, a drain region, and a gate, wherein the gate is over a channel region in a substrate between the source region and the drain region to include a gate metal, a gate dielectric layer, and a ferroelectric layer; a sensing layer conductively connected to the gate metal of the gate; and a bio layer on a top surface of the sensing layer. A method of manufacturing the biosensor structure is also provided.

Abstract: A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.

Abstract: A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.

Abstract: One or more devices and/or methods provided herein relate to a method for fabricating a semiconductor device, and more particularly for fabricating at least a portion of a vertical transport field effect transistor. The semiconductor device comprises a field-effect transmitter comprising a substrate, a fin extending outwardly from the substrate, a source/drain region having a first portion disposed between the substrate and the fin and stacked with the fin and the substrate along a common extension direction of the fin, and an excess section of semiconductor material disposed adjacent the first portion of the source/drain region and positioned other than stacked together with the substrate and the fin, wherein the semiconductor material of the excess section is different from a material of the fin and different from a material of the source/drain region.

Abstract: A semiconductor structure includes a source/drain region having a recessed portion. The semiconductor structure further includes a metal contact having a first portion and a second portion. The first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width. At least a portion of the second portion of the metal contact is disposed in the recessed portion of the source/drain region.

Abstract: A semiconductor structure comprises a vertical transistor, a first contact connecting to a source/drain region at a first side of the vertical transistor, a second contact extending from the first side of the vertical transistor to a second side of the vertical transistor, and an interconnect structure at the first side of the vertical transistor connecting the first contact to the second contact.

Abstract: A semiconductor device is provided that includes a transistor in which a self-aligned backside dielectric structure is in contact with one of the source/drain regions of the transistors and a self-aligned backside source/drain contact structure is in electrical contact with the other source/drain region of the transistor.

Abstract: A semiconductor structure is provided that includes a MOL and/or BEOL structure for low resistance, low capacitance and design flexibility. The structure includes a first metal level including a plurality of first metal lines and a plurality of first metal vias located at same level within a first interlayer dielectric material layer, and a second metal level located above the first metal level. The second metal level includes a plurality of second metal lines and a plurality of second metal vias located at a same level within a second interlayer dielectric material layer. The first metal level is formed utilizing a damascene process and the second metal level is formed utilizing a substrative etch. A single metallization is used to provide the first and second metal levels.

Abstract: Semiconductor devices having a direct backside contact are provided. In one aspect, a semiconductor device includes: at least one FET on a frontside of a wafer, where the wafer includes a semiconductor layer, and where a most backside-facing surface of the semiconductor layer is planar; and a backside contact disposed on the most backside-facing surface of the semiconductor layer, where the backside contact directly contacts source/drain regions of the at least one FET. A local wiring layer can be disposed on a most backside-facing surface of the backside contact. A method of fabricating the present semiconductor devices is also provided.

Abstract: A semiconductor device includes a substrate having a frontside, a backside, and a transistor that includes a gate region, a first source/drain region of a first depth into the substrate, and a second source/drain region of a second depth into the substrate. The semiconductor device further includes a backside contact (BC) region extending from the backside into the substrate and electrically connected to the first source/drain region. The semiconductor device further includes a backside partial diffusion break (BPDB) region that includes a non-conducting material, extending from the backside into the substrate and distinct from the first source/drain region.

Abstract: A semiconductor structure including a dielectric bar arranged between and physically separating a first source drain region from a second source drain region, where a height of the first source drain region is less than a height of the second source drain region, and a backside source drain contact directly beneath and in electrical communication with the second source drain region.

Abstract: A semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. The interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.

Abstract: Three dimensional electronic structures are provided in which ferromagnetic elements are present in both a first substrate and a second substrate to provide self-aligned contact of metal wiring that is present in the first substrate and the second substrate.

Abstract: A semiconductor structure includes a stacked device structure containing a first device and a second device over the first device in a stacked configuration. The semiconductor structure further includes a first backside contact connected to the first device and a first backside power line. The semiconductor structure further includes a second backside contact connected to the second device and a second backside power line.

Abstract: Interconnect designs with reduced via resistance are provided. In one aspect, an interconnect structure includes: at least a first metal line and a second metal line; and a conductive via in between the first metal line and the second metal line, wherein the conductive via has elongated dimensions along a major axis of the first metal line and along a major axis of the second metal line. Dielectric caps can be present on the first metal lines, and below and above the second metal lines. A method of forming the present interconnect structure is also provided.

Abstract: A semiconductor integrated circuit device is described. The device may include a semiconductor base, a source/drain region directly connected to a plurality of channels and directly connected to a portion of a first sidewall of the semiconductor base. The device may further include a backside contact directly connected to the S/D region and directly connected to a remaining portion of the first sidewall of the semiconductor base. The device may further include a backside contact plug directly connected to a second sidewall of semiconductor base. The backside contact plug substantially prevents electrical current from the S/D region through the semiconductor base.

Abstract: A semiconductor integrated circuit (IC) device is described. The device includes a transistor with a plurality of channels, a gate around each of the plurality of channels, a first source/drain (S/D) region, and a second S/D region. The device also includes a retained semiconductor substrate structure in direct contact with the first S/D region and with the second S/D region. The device further includes a wraparound backside contact in direct contact with the retained semiconductor substrate structure and in direct contact with the first S/D region.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a device layer having a frontside and a backside and including a transistor that includes a source/drain region at the backside of the device layer; a first and a second backside metal line with the source/drain region at least partially overlapping vertically with the first backside metal line and not overlapping vertically with the second backside metal line; and a backside local interconnect that conductively connects the source/drain region of the transistor with the second backside metal line, where the backside local interconnect includes a first portion and a second portion, the first portion horizontally extending from an area underneath the source/drain region to an area outside the source/drain region of the transistor, the second portion vertically connecting the first portion to the second backside metal line. Methods for forming the same are also provided.

Abstract: A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.