Abstract: A memory structure that includes a dielectric stack of a ferroelectric dielectric layer and a paraelectric dielectric layer. At least the ferroelectric dielectric layer produces a negative capacitance to amplify an applied voltage. A thickness of the ferroelectric dielectric layer and the paraelectric dielectric layer results in simultaneous breakdown of a dielectric material in each of the ferroelectric dielectric layer and the paraelectric dielectric layer for the formation of conductive filaments upon being exposed to an electric field produced by the applied voltage amplified by the negative capacitance. The memory structure also includes a first electrode at a first end of the dielectric stack, and a second electrode at a second end of the dielectric stack. The applied voltage is applied to the memory structure through at least one of the first electrode and the second electrode.

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. A first gap exists between the first backside signal line and the second backside signal line.

Abstract: A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.

Abstract: A first source drain region directly adjacent to a first nanosheet stack, a second source drain region directly adjacent to a second nanosheet stack, an inner electrode of a capacitor between the first source drain region and the second source drain region and a non-conducting layer sandwiched between the inner electrode and the first source drain region. A first source drain region directly adjacent to a first nanosheet stack, a second source drain region directly adjacent to a second nanosheet stack, an inner electrode of a capacitor between the first source drain region and the second source drain region, a first liner sandwiched between the inner electrode and the first source drain region, and a second liner sandwiched between the inner electrode and the second source drain region.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first source/drain (S/D) electrically connected to a backside contact on a backside. A device may include a second S/D electrically connected to a frontside contact on a frontside. A device may include a channel comprising a bottom dielectric isolation (BDI) between the first S/D and the second S/D. A device may include a backside interlayer dielectric (BILD) protruding past the BDI into direct contact with the second S/D. A device may include a residual silicon between the BILD and the backside contact.

Abstract: One or more systems, devices, and/or methods of use provided herein relate to a semiconductor device with separate power supplies for front side and backside stacked power distribution. A semiconductor device can include one or more circuits, a first power supply, a second power supply, and a third power supply. The first power supply can be disposed on a first side of the one or more circuits. The second power supply can be disposed on the first side of the one or more circuits. Further, the third power supply can be disposed on a second side of the one or more circuits. Additionally, the first side of the one or more circuits can be opposite to the second side of the one or more circuits.

Abstract: An interconnect device has a first layer with a first metal line, a second metal line, and a third metal line, a second layer with a metal jumper and a metal via. The metal jumper is electrically connected to the first metal line and the second metal line. The metal via is electrically connected to the second metal line, and the metal jumper and the metal via are electrically isolated. The interconnect device further includes a third layer with a fourth metal line. The metal jumper is electrically isolated from the third metal line by a first dielectric region between the metal jumper and the third metal line.

Abstract: A nanosheet semiconductor structure including a backside contact structure, top semiconductor layer adjacent to, and in electrical contact with, a bottom portion of the backside contact structure, and sidewall spacers between and physically separating a top portion of the backside contact structure from the top semiconductor layer.

Abstract: A semiconductor device includes a substrate and a transistor positioned on the substrate. The transistor includes transistor includes a channel region, a shared gate region, and a source and drain region. The source and drain region includes a concave outer wall includes a concave outer wall. A method of manufacturing a semiconductor device includes providing a substrate and forming a plurality of transistor gate structures on the substrate. A source and drain region are formed and positioned adjacent the plurality of transistor gate structures. A concave wall is recessed into material of the source and drain region toward a centerline of the source and drain region.

Abstract: A microelectronic structure including a plurality of nanosheet transistors. Each of the plurality of nanosheet transistors includes an active gate located around a plurality of active channel layers and each of the plurality of nanosheet transistors includes a source/drain region have a first length. The first length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. A power via located between a first dummy device and a second dummy device and the power via has second length. The second length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. The second length is larger than the first length.

Abstract: Embodiments of present invention provide a biosensor structure. The biosensor structure includes a substrate having a frontside and a backside opposing the frontside; a sensing surface at the frontside of the substrate, the sensing surface being adapted to detect certain biomolecules in a test solution placed on the sensing surface; and a controlling surface at the backside of the substrate, the controlling surface providing access to a controlling terminal, and the controlling terminal being capacitively connected to the sensing surface. A method of forming the same is also provided.

Abstract: Embodiments of present invention provide a biosensor structure. The biosensor structure includes a sensing transistor having a source region, a drain region, and a gate, wherein the gate is over a channel region in a substrate between the source region and the drain region to include a gate metal, a gate dielectric layer, and a ferroelectric layer; a sensing layer conductively connected to the gate metal of the gate; and a bio layer on a top surface of the sensing layer. A method of manufacturing the biosensor structure is also provided.

Abstract: A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.

Abstract: A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.

Abstract: One or more devices and/or methods provided herein relate to a method for fabricating a semiconductor device, and more particularly for fabricating at least a portion of a vertical transport field effect transistor. The semiconductor device comprises a field-effect transmitter comprising a substrate, a fin extending outwardly from the substrate, a source/drain region having a first portion disposed between the substrate and the fin and stacked with the fin and the substrate along a common extension direction of the fin, and an excess section of semiconductor material disposed adjacent the first portion of the source/drain region and positioned other than stacked together with the substrate and the fin, wherein the semiconductor material of the excess section is different from a material of the fin and different from a material of the source/drain region.

Abstract: A semiconductor structure includes a source/drain region having a recessed portion. The semiconductor structure further includes a metal contact having a first portion and a second portion. The first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width. At least a portion of the second portion of the metal contact is disposed in the recessed portion of the source/drain region.

Abstract: A semiconductor structure comprises a vertical transistor, a first contact connecting to a source/drain region at a first side of the vertical transistor, a second contact extending from the first side of the vertical transistor to a second side of the vertical transistor, and an interconnect structure at the first side of the vertical transistor connecting the first contact to the second contact.

Abstract: A semiconductor device is provided that includes a transistor in which a self-aligned backside dielectric structure is in contact with one of the source/drain regions of the transistors and a self-aligned backside source/drain contact structure is in electrical contact with the other source/drain region of the transistor.

Abstract: A semiconductor structure is provided that includes a MOL and/or BEOL structure for low resistance, low capacitance and design flexibility. The structure includes a first metal level including a plurality of first metal lines and a plurality of first metal vias located at same level within a first interlayer dielectric material layer, and a second metal level located above the first metal level. The second metal level includes a plurality of second metal lines and a plurality of second metal vias located at a same level within a second interlayer dielectric material layer. The first metal level is formed utilizing a damascene process and the second metal level is formed utilizing a substrative etch. A single metallization is used to provide the first and second metal levels.

Abstract: Semiconductor devices having a direct backside contact are provided. In one aspect, a semiconductor device includes: at least one FET on a frontside of a wafer, where the wafer includes a semiconductor layer, and where a most backside-facing surface of the semiconductor layer is planar; and a backside contact disposed on the most backside-facing surface of the semiconductor layer, where the backside contact directly contacts source/drain regions of the at least one FET. A local wiring layer can be disposed on a most backside-facing surface of the backside contact. A method of fabricating the present semiconductor devices is also provided.