Abstract: A semiconductor device is provided including a self-aligned backside contact structure located in a diffusion break region in which the backside contact structure electrically connects to a sidewall of a source/drain region of a transistor in at least one device region. Notably, the self-aligned backside contact structure of the present application lowers the device resistance and increases the current drive in the backside contacted transistor without capacitance penalty.

Abstract: A semiconductor device includes an active region layer having source/drain regions laterally disposed relative to one another in a row and having a zone bounded between adjacent source/drain regions. An embedded jumper is electrically connected to two adjacent source/drain regions within the zone.

Abstract: A semiconductor device includes a gate region, an active region surrounded by the gate region, at least one source/drain region, and a backside contact below the at least one source/drain region and having a first portion with a first height. A length of the first portion along the active region is smaller than a length of the active region.

Abstract: A semiconductor structure comprising a first circuit row and a second circuit row adjacent the first circuit row. The first circuit row comprises a first circuit cell and a second circuit cell, the first circuit cell having a first cell height greater than a first row height of the first circuit row, the second circuit cell having a second cell height different than the first cell height. The second circuit row comprises a third circuit cell, the third circuit cell having a third cell height less than a second row height of the second circuit row. The first circuit cell in the first circuit row is at least partially aligned with the third circuit cell in the second circuit row.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment and a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring. A distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.

Abstract: A semiconductor device includes a first stacked field-effect transistor structure having a first lower field-effect transistor device and a first upper field-effect transistor device. The semiconductor device also includes a second stacked field-effect transistor structure comprising a second lower field-effect transistor device and a second upper field-effect transistor device, where at least one of: the first lower field-effect transistor device includes a different number of channel layers than the second lower field-effect transistor device; and the first upper field-effect transistor device includes a different number of channel layers than the second upper field-effect transistor device.

Abstract: A skip-level via structure is provided that electrically connects a third level of interconnect wiring to a first level of interconnect wiring or a fourth level of interconnect wiring to a first level of interconnect wiring. In the first instance, the skip-level via structure enables connection even when the first level of interconnect wiring and the third level of interconnect wiring do not line up. In the second instance, the skip-level via structure enables a low resistance connection of the fourth level of interconnect wiring to the first level of interconnect wiring due to increased contact area.

Abstract: A semiconductor device includes a through layer skip via that traverses an intermediary metal layer. The through layer skip via has a damascene metal portion and a subtractive metal portion. A dielectric spacer is disposed within a thickness of the intermediary metal layer and surrounds a top portion of the subtractive metal portion.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a skip via. The skip via includes a first skip via segment vertically connected to a second skip via segment. The first skip via segment has a first width and the second skip via segment has a second width.

Abstract: Sacrificial test structures for testing with advanced packaging are provided. In one aspect, a device includes: a product structure having vias; and an etch-stop layer disposed on the product structure in between the vias, such that a surface of the etch-stop layer is coplanar with surfaces of the vias. A sacrificial test structure can be employed over the product structure, with the etch-stop layer therebetween. A method for using the present product structures is also provided.

Abstract: A semiconductor device includes a vertical bipolar junction device, having a collector, a base over the collector, an emitter over the base, one or more source/drain region/dummy and dummy gate alternatively and laterally extended over the emitter, and a contact over source/drain regions of the one or more source/drain region/dummy gate.

Abstract: Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a back-end-of-line (BEOL) region at a first side of a wafer. A backside region is at a second side of the wafer that is opposite the first side of the wafer. A set of signal lines are in the BEOL region, and a set of power rails are in the backside region. The set of signal lines includes a substantially constant signal-line pitch between each signal line in the set of signal lines. The set of power rails includes a substantially varying power-rail pitch between each power rail in the set of power rails.

Abstract: An interconnect structure includes a first metal layer comprising at least one metal wire with a first segment and a local extension having a width in a first direction that is larger than a width of the first segment. A second metal layer is on top or below the first metal layer comprising at least one metal wire. A via is connected between the at least one metal wire of the first metal layer and the at least one metal wire of the second metal layer. A width of the via in the first direction is larger than the width of the first segment but smaller than a width of the second segment.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a first metal line, a second metal line, and a third metal line running along a first orientation within a metal level, where the second metal line is located between the first and third metal lines. The semiconductor interconnect structure further includes a metal line connector running along a second orientation within the metal level. The metal line connector is located below the second metal line, and connected to the first and third metal lines.

Abstract: A nanosheet semiconductor structure including a backside contact structure beneath a first source drain region, and a bottom inner spacer directly beneath a second source drain region adjacent to the backside contact structure.

Abstract: An integrated circuit includes a first cell of a first cell height having a first feature and a second cell of a second cell height having a second feature corresponding to the first feature. The first cell height is greater than the second cell height. A transition region borders the first cell and the second cell. The transition region includes a change in dimension between the first feature and the second feature.

Abstract: A semiconductor structure with a first backside metal level that has a plurality of first type of lines and at least one second type line. The first type of lines have a wider top surface than the bottom surface and have a first width. The first type of lines each connect by a first via to a second backside metal level. Each of first type of lines and the second type line connect by a second via to a through-silicon via. The second type line is narrower than the first type of lines. Each of the second type line is between adjacent first type of lines. The second type line has a top surface that is in the middle of the first type of lines, below the first type of lines, above, or level with the top surface of the first type of lines.

Abstract: An interconnect structure for connecting an upper wiring line to a lower wiring line includes a via connecting a lower portion of the upper wiring line with an upper surface of the lower wiring line and a wrap-around via portion formed integrally with the via, the wrap-around portion extending along and electrically contacting a portion of the sides of the lower wiring line.

Abstract: A semiconductor structure with extended backside connections is provided.

Abstract: According to an embodiment of the present invention, a semiconductor device includes a flexible layer substrate. A plurality of ferromagnetic fill regions extend through the flexible layer substrate. A product chip is located under the flexible layer substrate. A plurality of ferromagnetic alignment marks extend through a portion of the product chip. The plurality of ferromagnetic fill regions and the plurality of ferromagnetic alignment marks are aligned through ferromagnetism.