Abstract: A semiconductor structure comprises a vertical transistor, a first contact connecting to a source/drain region at a first side of the vertical transistor, a second contact extending from the first side of the vertical transistor to a second side of the vertical transistor, and an interconnect structure at the first side of the vertical transistor connecting the first contact to the second contact.

Abstract: A semiconductor apparatus includes a substrate; a first conductive feature disposed on the substrate, the first conductive feature comprising a conductive material; a second conductive feature disposed on the substrate, the second conductive feature comprising the conductive material; a dielectric material at least partially surrounding the first conductive feature and the second conductive feature; and an interconnect between the first conductive feature and the second conductive feature, the interconnect comprising the conductive material integral with the first conductive feature and the second conductive feature and extending through the dielectric material and below the first conductive feature and the second conductive feature.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

Abstract: A field effect device is provided. The field effect device includes an active gate structure, a gate contact within the active gate structure, wherein the gate contact is the same height as the active gate structure, and a gate cut dielectric on opposite sides of the gate contact and active gate structure.

Abstract: Interconnect designs with reduced via resistance are provided. In one aspect, an interconnect structure includes: at least a first metal line and a second metal line; and a conductive via in between the first metal line and the second metal line, wherein the conductive via has elongated dimensions along a major axis of the first metal line and along a major axis of the second metal line. Dielectric caps can be present on the first metal lines, and below and above the second metal lines. A method of forming the present interconnect structure is also provided.

Abstract: Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

Abstract: A semiconductor array structure includes a substrate; a plurality of field effect transistors (FETs) arranged in rows and located on the substrate, each comprising a first source-drain region, a second source-drain region, at least one channel coupling the source-drain regions, and a gate adjacent the at least one channel. A plurality of frontside signal lines are on a front side of the FETs; a plurality of backside power rails are on a back side of the FETs; a plurality of backside signal wires are on the back side. Frontside signal connections run from the frontside signal lines to the first source-drain regions; Power connections run from the backside power rails to the second source-drain regions; and backside gate contact connections run from the backside signal wires to the gates. The backside gate contact connections each have a bottom dimension larger than the gate length.

Abstract: An integrated circuit includes a semiconductor substrate; a logic area, located outward of the semiconductor substrate; and a physically unclonable function (PUF) area, located outward of the semiconductor substrate. The logic area includes a plurality of logic metal-insulator-metal decoupling capacitors with at least three plates. The PUF area includes a plurality of PUF metal-insulator-metal capacitors with at least three plates. Shorts and opens are avoided in the logic area, while the PUF metal-insulator-metal capacitors exhibit deliberately-introduced shorts and opens that function as a PUF.

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

Abstract: A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Abstract: A semiconductor structure includes a common substrate; a first forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate and that has an nFET (n-doped Field Effect Transistor) and a pFET (p-doped Field Effect Transistor) and has a first ? (effective width ratio) between the nFET and the pFET; and a second forksheet device that is adjacent to the first forksheet device on the common substrate and that has a second ? between a second nFET and a second pFET. The second ? is different than the first ? by at least 5 percent. Another semiconductor structure includes a common substrate; a forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate; and a gate-all-around (GAA) nanosheet CMOS device that is located on the common substrate and is adjacent to the forksheet device.

Abstract: A complementary metal oxide semiconductor (CMOS) device. The device includes a pFET epi and an nFET epi. The pFET epi includes a single dielectric layer that wraps around a first portion of the pFET epi and a confined trench epi on a second portion of the pFET epi that is adjacent a first contact. The nFET epi includes a bi-layer dielectric liner that wraps around a first portion of the nFET epi and a second portion of the nFET epi that is adjacent a second contact.

Abstract: A system includes probe pins each including a probe tip and a plurality of thermocouples arranged such that at least one thermocouple is positioned between a pair of the probe pins. The plurality of thermocouples can be placed adjacent or above a device under test (DUT). The probe tips of the probe pins are placed over a plurality of pads. The plurality of thermocouples are placed adjacent or between the plurality of pads. The at least one thermocouple positioned between the pair of the probe pins can be either a single thermocouple or a thermocouple array.

Abstract: A transistor structure includes a semiconductor substrate; an NFET channel structure atop the substrate; a PFET channel structure atop the substrate; a first dielectric atop the PFET channel structure; a second dielectric atop the NFET channel structure; a shared internal metal gate atop the dielectrics; a shared ferroelectric layer atop the shared internal metal gate; and a shared external gate electrode atop the shared ferroelectric layer. The first and second dielectrics are doped with different metals that provide differing overall work functions for the PFET and the NFET. A method for making a transistor structure includes depositing a shared dielectric onto an NFET channel structure and a PFET channel structure, and converting the shared dielectric to a first high-k dielectric atop the PFET channel structure and a second high-k dielectric atop the NFET channel structure. The first high-k dielectric and the second high-k dielectric are doped with different metals.

Abstract: A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region. The CFET may further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.

Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.

Abstract: A semiconductor structure includes a source/drain region having a recessed portion. The semiconductor structure further includes a metal contact having a first portion and a second portion. The first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width. At least a portion of the second portion of the metal contact is disposed in the recessed portion of the source/drain region.

Abstract: A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further includes a source/drain region contact in physical contact with the V shaped internal recess, with the front surface, and with the rear surface. The device may be fabricated by forming the source/drain region, recessing the source/drain region, and by forming a sacrificial source/drain region upon and around the recessed source/drain region. The sacrificial source/drain region may be removed and the source/drain region contact may be formed in place thereof.

Abstract: A testing apparatus comprises a first electromagnet. The first electromagnet can be configured to expose a first test device to a first electromagnetic field. The testing apparatus also comprises a second electromagnet. The second electromagnet can be configured to expose a second test device to a second electromagnetic field.