Abstract: The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract: The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided and a base-connecting area of the second conductivity type is provided above the base area. An insulating area is provided above the base-connecting area and a window is formed in the insulating area and the base-connecting area so as to at least partly expose the base area. An insulating sidewall spacer is provided in the window in order to insulate the base-connecting area. An emitter layer which forms a monocrystalline emitter area above the base area and a polycrystalline emitter area above the insulating area and the sidewall spacer is differentially deposited and structured, and a tempering step is carried out.

Abstract: A reactor configuration contains a housing connected to a silicon wafer. The silicon wafer has pores extending from a first main area of the silicon wafer into an interior of the silicon wafer, preferably as far as a second main area of the silicon wafer. A catalyst layer at least partly covers the surface of the pores.

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract: The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.

Abstract: The method according to the invention makes it possible to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.

Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

Abstract: The silicon bipolar transistor (100) comprises a base, with a first highly-doped base layer (105) and a second poorly-doped base layer (106) which together form the base. The emitter is completely highly-doped and mounted directly on the second base layer (106).

Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

Abstract: An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.

Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

Abstract: A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A contact is disposed in the substrate and connects the capacitor to the MOS transistor.

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract: Significant amounts of pattern distortion were found to be the result of reflowing borophosphosilicate glass (BPSG) and silicon dioxide shrinkage during high temperature junction anneals. In order to remedy this problem, a method for suppressing the pattern distortion by subjecting the wafer coated with BPSG and with silicon dioxide layers to a high temperature anneal before patterning is disclosed. The high temperature anneal densifies the undoped silicon dioxide before patterning, so that shrinkage of the undoped silicon dioxide does not affect the patterning steps.

Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

Abstract: A method for producing a microelectronic structure is suggested in which a layer structure (30) which partially covers a substrate (5) and which comprises at least one first conductive layer (15,20) which reaches to a side wall (35) of the layer structure (30), is covered with a second conductive layer (45). The second conductive layer (45) is then subsequently back-etched to as great an extent as possible with an etching process with physical delamination, wherein delaminated material deposits on the side wall (35) of the layer structure (30). On the side wall (35) the delaminated material forms a protection layer (60) by means of which the first conductive layer (15,20) is to be protected from attack by oxygen to the furthest extent possible.

Abstract: A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.