Abstract: A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

Abstract: A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

Abstract: A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A contact is disposed in the substrate and connects the capacitor to the MOS transistor.

Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Abstract: An integrated circuit configuration includes a structure, a p-n junction, and a defect plane disposed such that each of a plurality of straight lines, that intersect or touch the structure and the p-n junction, intersect the defect plane. This prevents unwanted leakage currents through the p-n junction and increases a retention time in a DRAM cell configuration. A wafer configuration and a method of producing an integrated circuit configuration are also provided.

Abstract: A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

Abstract: A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

Abstract: A method for the fabrication of a doped silicon layer, includes carrying out deposition by using a process gas containing SiH4, Si2H6 and a doping gas. The doped silicon layer which is thus produced can be used both as a gate electrode of an MOS transistor and as a conductive connection. At a thickness between 50 and 200 nm it has a resistivity less than or equal to 0.5 m&OHgr;cm.

Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

Abstract: In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

Abstract: For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective epitaxy. Structure sizes below 100 nm can be realized in the statistical mask. Surface enlargement factors up to 60 are thus achieved.

Abstract: A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

Abstract: On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.

Abstract: A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

Abstract: For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

Abstract: The DRAM cell arrangement comprises, per memory cell, a vertical MOS transistor whose first source/drain region is connected to a storage node of a storage capacitor, whose channel region (3) is annularly enclosed by a gate electrode (13) and whose second source/drain region is connected to a buried bit line. The DRAM cell arrangement is produced using only two masks, with the aid of a spacer technique, with a memory cell area of 2F.sup.2, where F is the minimum structure size which can be produced using the respective technology.

Abstract: For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

Abstract: A bottle-shaped trench capacitor having an expanded lower trench portion with an epi layer therein. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the expanded lower trench portion to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.