Abstract: Silicon carbide substrate wafers are prepared by transferring a monocrystalline silicon layer from a donor wafer onto a handle wafer, the silicon layer being implanted with carbon and annealed to form a monocrystalline SiC layer prior to or after transfer of the silicon layer.

Abstract: An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the condition v/G<(v/G)crit=1.3×10?3 cm2/(K·min) being fulfilled at the crystallization front over the entire crystal cross section, with the result that an excess of interstitial silicon atoms prevails in the silicon single crystal produced; separation of at least one donor wafer from this silicon single crystal, bonding of the donor wafer to a carrier wafer, and reduction of the thickness of the donor wafer, with the result that a silicon layer having a thickness of less than 500 nm bonded to the carrier wafer remains.

Abstract: Silicon carbide substrate wafers are prepared by transferring a monocrystalline silicon layer from a donor wafer onto a handle wafer, the silicon layer being implanted with carbon and annealed to form a monocrystalline SiC layer prior to or after transfer of the silicon layer.

Abstract: The invention relates to a process for manufacturing a multilayered semiconductor wafer comprising a handle wafer (5) and a layer (40) comprising silicon carbide bonded to the handle wafer (5), the process comprising the steps of: a) providing a handle wafer (5), b) providing a donor wafer (1) comprising a donor layer (2) and a remainder (3) of the donor wafer, the donor layer (2) comprising monocrystalline silicon, e) bonding the donor layer (2) of the donor wafer (1) to the handle wafer (5), and f) removing the remainder (3) of the donor wafer in order to expose the donor layer (2) which remains bonded to the handle wafer (5), the process being characterized by further steps of c) implanting carbon ions into the donor layer (2) in order to produce a layer (4) comprising implanted carbon, and d) heat-treating the donor layer (2) comprising the layer (4) comprising implanted carbon in order to form a silicon carbide donor layer (44) in at least part of the donor layer (2).

Abstract: To reduce and homogenize the thickness of a semiconductor layer which lies on the surface of an electrically insulating material, the surface of the semiconductor layer is exposed to the action of an etchant whose redox potential is adjusted as a function of the material and the desired final thickness of the semiconductor layer, so that the material erosion per unit time on the surface of the semiconductor layer due to the etchant becomes less as the thickness of the semiconductor layer decreases, and is only from 0 to 10% of the thickness per second when the desired thickness is reached. The method is carried out without the action of light or the application of an external electrical voltage.

Abstract: A silicon wafer having no epitaxially deposited layer or layer produced by joining to the silicon wafer, with a nitrogen concentration of 1·1013-8·1014 atoms/cm3, an oxygen concentration of 5.2·1017-7.5·1017 atoms/cm3, a central thickness BMD density of 3·108-2·1010 cm?3, a cumulative length of linear slippages ?3 cm and a cumulative area of areal slippage regions ?7 cm2, the front surface having <45 nitrogen-induced defects of >0.13 ?m LSE in the DNN channel, a layer at least 5 ?m thick, in which ?1·104 COPs/cm3 with a size of ?0.09 ?m occur, and a BMD-free layer ?5 ?m thick. Such wafers may be produced by heat treating the silicon wafer, resting on a substrate holder, a specific substrate holder used depending on the wafer doping. For each holder, maximum heating rates are selected to avoid formation of slippages.

Abstract: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 ?m, a DeltaWarp of less than 30 ?m, a bow of less than 10 ?m and a DeltaBow of less than 10 ?m. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

Abstract: A process for producing a semiconductor substrate comprising a carrier wafer and a layer of single-crystalline semiconductor material: a) producing a layer containing recesses at the surface of a donor wafer of single-crystalline semiconductor material, b) joining the surface of the donor wafer containing recesses to the carrier wafer, c) heat treating to close the recesses at the interface between the carrier wafer and the donor wafer to form a layer of cavities within the donor wafer, and d) splitting the donor wafer along the layer of cavities, resulting in a layer of semiconductor material on the carrier wafer. Semiconductor substrates prepared thusly may have a single-crystalline semiconductor layer having a thickness of 100 nm or less, a layer thickness uniformity of 5% or less, and an HF defect density of 0.02/cm2 or less.

Abstract: Treatment of a semiconductor wafer employs: a) position-dependent measuring of a parameter characterizing the semiconductor wafer to determine a position-dependent value of the parameter over an entire surface of the semiconductor wafer, b) oxidizing the entire surface of the semiconductor wafer under the action of an oxidizing agent with simultaneous exposure of the entire surface, the oxidation rate and thus the thickness of the resulting oxide layer dependent on the light intensity at the surface of the semiconductor wafer, and c) removing of the oxide layer, the light intensity in step b) predefined in a position-dependent manner such that differences in the position-dependent values of the parameter measured are reduced by the position-dependent oxidation rate resulting in step b) and subsequent removal of the oxide layer in step c).

Abstract: The invention relates to a process for manufacturing a multilayered semiconductor wafer comprising a handle wafer (5) and a layer (40) comprising silicon carbide bonded to the handle wafer (5), the process comprising the steps of: a) providing a handle wafer (5), b) providing a donor wafer (1) comprising a donor layer (2) and a remainder (3) of the donor wafer, the donor layer (2) comprising monocrystalline silicon, e) bonding the donor layer (2) of the donor wafer (1) to the handle wafer (5), and f) removing the remainder (3) of the donor wafer in order to expose the donor layer (2) which remains bonded to the handle wafer (5), the process being characterized by further steps of c) implanting carbon ions into the donor layer (2) in order to produce a layer (4) comprising implanted carbon, and d) heat-treating the donor layer (2) comprising the layer (4) comprising implanted carbon in order to form a silicon carbide donor layer (44) in at least part of the donor layer (2).

Abstract: A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon wafer by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ Oi ] < [ Oi ] eq ? ( T ) ? exp ? 2 ? ? SiO ? ? 2 ? ? rkT is satisfied, where [Oi] is an oxygen concentration in the silicon wafer, [Oi]eq(T) is a limit solubility of oxygen in silicon at a temperature T, ?SiO2 is the surface energy of silicon dioxide, ? is a volume of a precipitated oxygen atom, r is a mean COP and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least part of the time being exposed to an oxygen-con

Abstract: A process for producing a semiconductor substrate comprising a carrier wafer and a layer of single-crystalline semiconductor material: a) producing a layer containing recesses at the surface of a donor wafer of single-crystalline semiconductor material, b) joining the surface of the donor wafer containing recesses to the carrier wafer, c) heat treating to close the recesses at the interface between the carrier wafer and the donor wafer to form a layer of cavities within the donor wafer, and d) splitting the donor wafer along the layer of cavities, resulting in a layer of semiconductor material on the carrier wafer. Semiconductor substrates prepared thusly may have a single-crystalline semiconductor layer having a thickness of 100 nm or less, a layer thickness uniformity of 5% or less, and an HF defect density of 0.02/cm2 or less.

Abstract: A process for producing a semiconductor substrate comprising a carrier wafer and a layer of single-crystalline semiconductor material: a) producing a layer containing recesses at the surface of a donor wafer of single-crystalline semiconductor material, b) joining the surface of the donor wafer containing recesses to the carrier wafer, c) heat treating to close the recesses at the interface between the carrier wafer and the donor wafer to form a layer of cavities within the donor wafer, and d) splitting the donor wafer along the layer of cavities, resulting in a layer of semiconductor material on the carrier wafer. Semiconductor substrates prepared thusly may have a single-crystalline semiconductor layer having a thickness of 100 nm or less, a layer thickness uniformity of 5% or less, and an HF defect density of 0.02/cm2 or less.

Abstract: SOI wafers are manufactured to have very thin device layers of high surface quality. The layer is ?20 nm in thickness, has an HF density of ?0.1/cm2, and a surface roughness of 0.2 nm RMS.

Abstract: To reduce and homogenize the thickness of a semiconductor layer which lies on the surface of an electrically insulating material, the surface of the semiconductor layer is exposed to the action of an etchant whose redox potential is adjusted as a function of the material and the desired final thickness of the semiconductor layer, so that the material erosion per unit time on the surface of the semiconductor layer due to the etchant becomes less as the thickness of the semiconductor layer decreases, and is only from 0 to 10% of the thickness per second when the desired thickness is reached. The method is carried out without the action of light or the application of an external electrical voltage.

Abstract: Semiconductor wafers are leveled by position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate. Semiconductor wafers with improved flatness and nanotopography, and SOI wafers with improved layer thickness homogeneity are produced by this process.

Abstract: An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the condition v/G<(v/G)crit=1.3×10?3 cm2/(K·min) being fulfilled at the crystallization front over the entire crystal cross section, with the result that an excess of interstitial silicon atoms prevails in the silicon single crystal produced; separation of at least one donor wafer from this silicon single crystal, bonding of the donor wafer to a carrier wafer, and reduction of the thickness of the donor wafer, with the result that a silicon layer having a thickness of less than 500 nm bonded to the carrier wafer remains.

Abstract: An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the condition v/G<(v/G)crit=1.3×10?3 cm2/(K·min) being fulfilled at the crystallization front over the entire crystal cross section, with the result that an excess of interstitial silicon atoms prevails in the silicon single crystal produced; separation of at least one donor wafer from this silicon single crystal, bonding of the donor wafer to a carrier wafer, and reduction of the thickness of the donor wafer, with the result that a silicon layer having a thickness of less than 500 nm bonded to the carrier wafer remains.

Abstract: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 ?m, a DeltaWarp of less than 30 ?m, a bow of less than 10 ?m and a DeltaBow of less than 10 ?m. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

Abstract: A semiconductor substrate useful as a donor wafer is a single-crystal silicon wafer having a relaxed, single-crystal layer containing silicon and germanium on its surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight, and a layer of periodically arranged cavities below the surface. The invention also relates to a process for producing this semiconductor substrate and to an sSOI wafer produced from this semiconductor substrate.