Abstract: A package structure and method for forming the same are provided. The package structure includes a top interposer formed over a substrate, and a first die formed over the top interposer. The first die includes an optical package structure, and the optical package structure includes first optical components. The first die also includes an electronic die bonded to the optical package structure to form a hybrid bonding structure. The hybrid bonding structure includes a metal-to-metal bonding and dielectric-to-dielectric bonding. The package structure includes an optical die adjacent to the first die, and the top interposer is shared by the optical die and the first die.

Abstract: A semiconductor device and method of manufacturing are disclosed. The semiconductor device includes an optical die, a laser die, and an interposer. The optical die has photonic integrated circuits (PICs), electronic integrated circuits (EICs), and one or more first coupling waveguides. The laser die has at least one laser diode and one or more second coupling waveguides. The optical die and the laser die are bonded to a first side of the interposer using a metal-to-metal bonding, where at least one of the one or more first coupling waveguides is optically aligned with at least one of the one or more second coupling waveguides. An optical glue fills a gap between the aligned at least one of the one or more first coupling waveguides and the at least one of the one or more second coupling waveguides.

Abstract: A semiconductor device includes first and second semiconductor fins, first, second, third and fourth gate structures, and a dielectric structure. The first semiconductor fin and the second semiconductor fin are over a substrate. The first gate structure and the second gate structure respectively extend across the first semiconductor fin and the second semiconductor fin. The first gate structure has a longitudinal axis aligned with a longitudinal axis of the second gate structure. The dielectric structure interposes the first gate structure and the second gate structure. The third gate structure extends across the first and second semiconductor fins. The fourth gate structure extends across the first and second semiconductor fins. The third gate structure is between the fourth gate structure and the dielectric structure. The third gate structure has a maximal width greater than a maximal width of the fourth gate structure.

Abstract: A semiconductor structure includes a substrate, a bonding structure disposed over the substrate, and a filling layer. The substrate includes an optically active region and an optical surface in the optically active region. The bonding structure includes a bonding dielectric layer and conductive features in the bonding dielectric layer and arranged outside a keep-out zone of the bonding structure, where in a first view, the keep-out zone is located in the optically active region, and a first feature of the conductive features is disposed between the optically active region and the keep-out zone. The filling layer is interposed between the bonding structure and the optically active region of the substrate. The first feature is separated from the filling layer by the bonding dielectric layer in a second view.

Abstract: Optical devices and methods of manufacture are presented in which metallization layers are formed over a first active layer of first optical components, a first opening is formed through the metallization layers, a first semiconductor die is bonded over the metallization layers, and a laser die is bonded over the metallization layers, wherein after the bonding the laser die a first mirror located within the laser die is aligned with a second mirror through the first opening.

Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Abstract: Optical devices and methods of manufacture are presented in which a resonant ring is incorporated with a optical device on an interposer substrate. The material for the resonant ring may be a material that can trigger second order non-linearity in received light or a material that can trigger third order non-linearity without electrical driving mechanisms.

Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.

Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.

Abstract: In some embodiments of the method, patterning the opening includes: projecting a radiation beam toward the second dielectric layer, the radiation beam having a pattern of the opening. In some embodiments of the method, the single-patterning photolithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with the conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form the first metal line from remaining portions of the conductive material, top surfaces of the first metal line and the second dielectric layer being planar after the planarizing.

Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Abstract: A semiconductor device includes first and second semiconductor fins, first, second, third and fourth gate structures, and a dielectric structure. The first semiconductor fin and the second semiconductor fin are over a substrate. The first gate structure and the second gate structure respectively extend across the first semiconductor fin and the second semiconductor fin. The first gate structure has a longitudinal axis aligned with a longitudinal axis of the second gate structure. The dielectric structure interposes the first gate structure and the second gate structure. The third gate structure extends across the first and second semiconductor fins. The fourth gate structure extends across the first and second semiconductor fins. The third gate structure is between the fourth gate structure and the dielectric structure. The third gate structure has a maximal width greater than a maximal width of the four gate structure.

Abstract: A semiconductor device includes a semiconductor fin, a gate cut region, a first gate structure and a second gate structure. The semiconductor fin extends from a substrate. The gate cut region extends in parallel with a longitudinal axis of the semiconductor fin and not overlaps the semiconductor fin. The first gate structure and the second gate structure extend across the semiconductor fin. The first gate structure is laterally between the gate cut region and the second gate structure along a direction parallel with the longitudinal axis of the semiconductor fin. The first gate structure has a greater width variation than the second gate structure.

Abstract: A memory device includes a plurality of memory cells located in a first region of the memory device. The memory cells include a first signal line, a first circuit located in the first region of the memory device, and a plurality of logic circuits located in a second region of the memory device. The second region and the first region have different design rules. The first circuit is configured to be selectively enabled and disabled. When the first circuit is enabled, the first signal line is electrically coupled in parallel with a second signal line.

Abstract: A memory device includes a plurality of memory cells located in a first region of the memory device. The memory cells include a first signal line, a first circuit located in the first region of the memory device, and a plurality of logic circuits located in a second region of the memory device. The second region and the first region have different design rules. The first circuit is configured to be selectively enabled and disabled. When the first circuit is enabled, the first signal line is electrically coupled in parallel with a second signal line.