Patents by Inventor Ren-Fen Tsui
Ren-Fen Tsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811321Abstract: A semiconductor device includes a substrate having a semiconductor fin, an isolation feature over the substrate and not overlapping the semiconductor fin, a first gate structure over the substrate, and a second gate structure over the substrate. The isolation feature is closer to the first gate structure than the second gate structure. The first gate structure has a maximum width greater than a maximum width of the second gate structure.Type: GrantFiled: August 5, 2019Date of Patent: October 20, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon-Jhy Liaw
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Publication number: 20200295014Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.Type: ApplicationFiled: June 3, 2020Publication date: September 17, 2020Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui
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Patent number: 10685967Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.Type: GrantFiled: May 20, 2019Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui
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Publication number: 20190363024Abstract: A semiconductor device includes a substrate having a semiconductor fin, an isolation feature over the substrate and not overlapping the semiconductor fin, a first gate structure over the substrate, and a second gate structure over the substrate. The isolation feature is closer to the first gate structure than the second gate structure. The first gate structure has a maximum width greater than a maximum width of the second gate structure.Type: ApplicationFiled: August 5, 2019Publication date: November 28, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dian-Sheg YU, Ren-Fen TSUI, Jhon-Jhy LIAW
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Publication number: 20190312040Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.Type: ApplicationFiled: June 24, 2019Publication date: October 10, 2019Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
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Publication number: 20190279992Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.Type: ApplicationFiled: May 20, 2019Publication date: September 12, 2019Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui
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Publication number: 20190252318Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
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Patent number: 10373879Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure over a substrate, forming gate spacers over the substrate, cutting the first dummy gate structure to form separated dummy gate portions, forming a dielectric feature between the dummy gate portions, and performing a thermal process to the dielectric feature to contract the dielectric feature, wherein the contraction of the dielectric feature deforms at least one of the gate spacers such that a distance between the gate spacers is increased.Type: GrantFiled: May 22, 2017Date of Patent: August 6, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon-Jhy Liaw
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Patent number: 10332896Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.Type: GrantFiled: January 15, 2018Date of Patent: June 25, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
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Patent number: 10297602Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.Type: GrantFiled: May 18, 2017Date of Patent: May 21, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui
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Patent number: 10269704Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.Type: GrantFiled: May 21, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
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Patent number: 10163494Abstract: A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.Type: GrantFiled: May 31, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bing-Chian Lin, Ren-Fen Tsui
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Publication number: 20180350431Abstract: A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Bing-Chian LIN, Ren-Fen TSUI
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Publication number: 20180337188Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.Type: ApplicationFiled: May 18, 2017Publication date: November 22, 2018Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui
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Publication number: 20180315853Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure over a substrate, forming gate spacers over the substrate, cutting the first dummy gate structure to form separated dummy gate portions, forming a dielectric feature between the dummy gate portions, and performing a thermal process to the dielectric feature to contract the dielectric feature, wherein the contraction of the dielectric feature deforms at least one of the gate spacers such that a distance between the gate spacers is increased.Type: ApplicationFiled: May 22, 2017Publication date: November 1, 2018Inventors: Dian-Sheg YU, Ren-Fen TSUI, Jhon-Jhy LIAW
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Publication number: 20180269151Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.Type: ApplicationFiled: May 21, 2018Publication date: September 20, 2018Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
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Patent number: 9978680Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.Type: GrantFiled: May 30, 2017Date of Patent: May 22, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
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Publication number: 20180138186Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.Type: ApplicationFiled: January 15, 2018Publication date: May 17, 2018Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
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Patent number: 9871046Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.Type: GrantFiled: July 5, 2016Date of Patent: January 16, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
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Patent number: 9805815Abstract: A bit cell includes a program device comprising a first source/drain region and a second source/drain region separated by a first channel. The first source/drain region, the second source/drain region, and the first channel are positioned along a first direction. The bit cell also includes an electrical fuse (eFuse) having a conduction path along the first direction. A conductive element is electrically connected with the first source/drain region and one end of the eFuse.Type: GrantFiled: August 18, 2016Date of Patent: October 31, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Hung Chen, Liang Chuan Chang, Wei-Fen Pai, Bai-Mei Chang, Shao-Yu Chou, Ren-Fen Tsui, Dian-Sheg Yu, Shih-Guo Shen