Patents by Inventor Ren-Fen Tsui

Ren-Fen Tsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10269704
    Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
  • Patent number: 10163494
    Abstract: A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bing-Chian Lin, Ren-Fen Tsui
  • Publication number: 20180350431
    Abstract: A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Bing-Chian LIN, Ren-Fen TSUI
  • Publication number: 20180337188
    Abstract: A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Inventors: Dian-Sheg Yu, Jhon Jhy Liaw, Ren-Fen Tsui
  • Publication number: 20180315853
    Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure over a substrate, forming gate spacers over the substrate, cutting the first dummy gate structure to form separated dummy gate portions, forming a dielectric feature between the dummy gate portions, and performing a thermal process to the dielectric feature to contract the dielectric feature, wherein the contraction of the dielectric feature deforms at least one of the gate spacers such that a distance between the gate spacers is increased.
    Type: Application
    Filed: May 22, 2017
    Publication date: November 1, 2018
    Inventors: Dian-Sheg YU, Ren-Fen TSUI, Jhon-Jhy LIAW
  • Publication number: 20180269151
    Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 20, 2018
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
  • Patent number: 9978680
    Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
  • Publication number: 20180138186
    Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.
    Type: Application
    Filed: January 15, 2018
    Publication date: May 17, 2018
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
  • Patent number: 9871046
    Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
  • Patent number: 9805815
    Abstract: A bit cell includes a program device comprising a first source/drain region and a second source/drain region separated by a first channel. The first source/drain region, the second source/drain region, and the first channel are positioned along a first direction. The bit cell also includes an electrical fuse (eFuse) having a conduction path along the first direction. A conductive element is electrically connected with the first source/drain region and one end of the eFuse.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hung Chen, Liang Chuan Chang, Wei-Fen Pai, Bai-Mei Chang, Shao-Yu Chou, Ren-Fen Tsui, Dian-Sheg Yu, Shih-Guo Shen
  • Publication number: 20170263555
    Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
    Type: Application
    Filed: May 30, 2017
    Publication date: September 14, 2017
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
  • Publication number: 20170243872
    Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.
    Type: Application
    Filed: July 5, 2016
    Publication date: August 24, 2017
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
  • Patent number: 9666587
    Abstract: A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw
  • Patent number: 7705464
    Abstract: The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to an improved connection structure for semiconductor devices. A connection structure for a semiconductor device includes: a peanut-shaped opening comprising a narrow area and one or more wide areas, wherein the narrow area is between two of the one or more wide areas; and a conductive plug for filling at least partially the peanut-shaped opening.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: April 27, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhon Jhy Liaw, Sung-Chun Hsieh, Wesley Lin, Chii-Ming W Wu, Ren-Fen Tsui
  • Publication number: 20070257323
    Abstract: A stacked contact structure includes a first contact plug of a first conductive material filling a first contact hole in a first dielectric layer, and a second contact plug of a second conductive material filling a second contact hole in a second dielectric layer. The second conductive material is different from the first conductive material, and the second conductive material has an electrical resistance lower than that of the first conductive material.
    Type: Application
    Filed: May 5, 2006
    Publication date: November 8, 2007
    Inventors: Ren-Fen Tsui, Jiaw-Ren Shih
  • Publication number: 20060055043
    Abstract: The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to an improved connection structure for semiconductor devices. A connection structure for a semiconductor device includes: a peanut-shaped opening comprising a narrow area and one or more wide areas, wherein the narrow area is between two of the one or more wide areas; and a conductive plug for filling at least partially the peanut-shaped opening.
    Type: Application
    Filed: September 13, 2004
    Publication date: March 16, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhon Liaw, Sung-Chun Hsieh, Wesley Lin, Chii-Ming Wu, Ren-Fen Tsui