Abstract: An anti-shake device for positioning an image-capturing unit in an optical instrument. A base includes a shaft pillar. A clamp unit includes a first clamping arm and a second clamping arm. The first and second clamping arms pivot to the shaft pillar of the base and detachably clamp the image-capturing unit. A drive unit is connected to the base and includes a driven member driving the first and second clamping arms of the clamp unit to rotate and shifting between a first mode and a second mode. The first and second clamping arms are separated from each other and the image-capturing unit when the driven member is in the first mode. The first and second clamping arms close and clamp the image-capturing unit when the driven member is in the second mode.

Abstract: A device is formed to include an interposer having a top surface, and a bump on the top surface of the interposer. An opening extends from the top surface into the interposer. A first die is bonded to the bump. A second die is located in the opening of the interposer and bonded to the first die.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: A method and an apparatus for deciding a traveling direction in a space are provided. After receiving a starting signal from a mobile apparatus, a network node of a network apparatus generates a request signal and sends it to a processing apparatus. Then the processing apparatus decides the traveling direction and sends a direction signal comprising the traveling direction to the nearest network node to instruct a moving apparatus to move. The method, and apparatus are more convenient and more cost-effective system than those in the prior art.

Abstract: A method and a system for network synchronization are provided. In this method, when a node attempts to join a network, a parent node is searched from all other nodes already joined the network per specific time interval. If the parent node can be found, sync-information sent by the parent node is received by the node so as to synchronize with the parent node and enter a working mode. When a sleeping instruction sent by the parent node is received, or a timer determines that a network ending time is reached according to the sync-information, the node switches to a sleeping mode. However, when the timer determines that a network wakeup time is reached according to the sync-information, the node attempts to join the network again. All nodes in the network can work and sleep simultaneously so as to extend the lifetime of the battery.

Abstract: A method and a system for recognizing the statuses of electric appliances are provided. In the present method, a loop is taking as a unit for recognition, and a power consumption factor sensor which is capable of measuring a single power consumption factor is used such that the current status of each electric appliance in the loop can be recognized by comparing the probability distribution of the power consumption factor. Since it is not needed to dispose an extra measuring device on each electric appliance, the cost of recognizing the statuses of the electric appliances is significantly reduced.

Abstract: A method and a system for recognizing power consumption behaviors of electric appliances in a loop are provided. When a variation value of a power consumption information of the loop exceeds a threshold, a current value of the power consumption information is served as a main loop factor value of the loop, and a similar combinative factor value close to the main loop factor value is looked up in a behavior-factor mapping table. If the similar combinative factor value is not found, the main loop factor value corresponding to a new power consumption behavior is obtained according to the variation value of the power consumption information to reconstruct the behavior-factor mapping table. After obtaining the similar combinative factor value from the behavior-factor mapping table, a current electric appliance power consumption behavior of the loop is determined according to a power consumption behavior combination corresponding to the similar combinative factor value.

Abstract: A method and a system for estimating use time of electric appliances are provided. In the present method, all time points corresponding to an appliance power on event or an appliance power off event are obtained according to a value-time curve of at least one electric characteristic. A characteristic value of each of the time points is calculated according to the value-time curve, so as to pair the time points corresponding to the appliance power off event with the time points corresponding to the appliance power on event appropriately. After the pairing process is accomplished, the use time of each of the electric appliances can be calculated by the paired time points and thereby the power consumption of the electric appliances can be figured out.

Abstract: A method and a system for network synchronization are provided. In this method, when a node attempts to join a network, a parent node is searched from all other nodes already joined the network per specific time interval. If the parent node can be found, sync-information sent by the parent node is received by the node so as to synchronize with the parent node and enter a working mode. When a sleeping instruction sent by the parent node is received, or a timer determines that a network ending time is reached according to the sync-information, the node switches to a sleeping mode. However, when the timer determines that a network wakeup time is reached according to the sync-information, the node attempts to join the network again. All nodes in the network can work and sleep simultaneously so as to extend the lifetime of the battery.

Abstract: An anti-shake device for positioning an image-capturing unit in an optical instrument. A base includes a shaft pillar. A clamp unit includes a first clamping arm and a second clamping arm. The first and second clamping arms pivot to the shaft pillar of the base and detachably clamp the image-capturing unit. A drive unit is connected to the base and includes a driven member driving the first and second clamping arms of the clamp unit to rotate and shifting between a first mode and a second mode. The first and second clamping arms are separated from each other and the image-capturing unit when the driven member is in the first mode. The first and second clamping arms close and clamp the image-capturing unit when the driven member is in the second mode.

Abstract: A method and an apparatus for deciding a traveling direction in a space are provided. After receiving a starting signal from a mobile apparatus, a network node of a network apparatus generates a request signal and sends it to a processing apparatus. Then the processing apparatus decides the traveling direction and sends a direction signal comprising the traveling direction to the nearest network node to instruct a moving apparatus to move. The method, and apparatus are more convenient and more cost-effective system than those in the prior art.

Abstract: A deploying apparatus, a method, and a computer readable medium thereof for deploying a network in a space are provided. The method generates a plurality of grid points in the space and then disposes a first network node having a first effective connection range on one of the grid points. After that the following rule can be repeated: if a new network node is required to be disposed, it has to be disposed on a grid point that covered by at least one of the effective connection ranges of the previous disposed network nodes. In addition, an effective connection range of the new network node has to cover one of the previous disposed network nodes. By using the technique, the network can be deployed rapidly without heavy calculation. Furthermore, when the setting of the space changes or when the number of the network nodes changes, the technique does not have to deploy the whole network in the space again. It only has to adjust the deployment of part of the network in the space.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A method for forming a semiconductor device having a reduced pitch is provided. A pad oxide layer is formed on a substrate, and a silicon nitride layer is formed on the pad oxide layer. A trimmed photoresist layer is formed on the silicon nitride layer, and the silicon nitride layer is etched using the trimmed photoresist layer as an etch mask. The trimmed photoresist layer is removed until the silicon nitride layer is completely exposed, and an exposed portion of the pad oxide layer is removed until a portion of the substrate is exposed. A gate oxide layer is formed on the exposed portion of the substrate. A poly layer is deposited on the silicon nitride layer, and the poly layer is etched back to form a plurality of poly gates. Then, the silicon nitride layer is removed.

Abstract: A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting in smaller and faster integrated circuits. In a preferred embodiment, a conductive layer, a stop layer, and a polysilicon layer are formed on a substrate. A patterned photoresist layer is formed on the polysilicon layer, and a first polymer layer is formed on surfaces of the photoresist layer. The first polymer layer is used as an etching mask to define the polysilicon layer, the stop layer, and the conductive layer. An oxide layer is formed on the substrate, and then the oxide layer is etched back until the polysilicon layer is exposed. The polysilicon layer is removed, and a second polymer layer is formed on surfaces of the oxide layer.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: The present invention provides a method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting in smaller and faster integrated circuits. In a preferred embodiment, a conductive layer, a stop layer, and a polysilicon layer are formed on a substrate. A patterned photoresist layer is formed on the polysilicon layer, and a first polymer layer is formed on surfaces of the photoresist layer. The first polymer layer is used as an etching mask to define the polysilicon layer, the stop layer, and the conductive layer. An oxide layer is formed on the substrate, and then the oxide layer is etched back until the polysilicon layer is exposed. The polysilicon layer is removed, and a second polymer layer is formed on surfaces of the oxide layer.