Abstract: A method is described which may be used to reduce a pitch between conductive features. One embodiment of the method involves forming a structure including a substrate, a conductive layer on the substrate, multiple photoresist features arranged on the conductive layer, a polymer layer on top surfaces and sidewalls of each of the photoresist features, and a material layer on and around the photoresist features and the polymer layers. An upper portion of the material layer is removed such that upper surfaces of the photoresist features and the polymer layer are exposed, and a remaining portion of the material layer remains. The polymer layer is removed, and the photoresist features and the remaining portion of the material layer are used as etch masks to pattern the conductive layer, thereby producing a number of conductive features. The photoresist features and the remaining portion of the material layer are removed.

Abstract: This invention relates to a method for fabricating a electrically insulating layer, more particularly, to the method for fabricating a electrically insulating layer by using the different etching rates in etching oxide and etching nitride. The present invention uses the way in different etching rates to etch oxide and nitride. When begin the etching process to fabricating the electrically insulating layer, the etching rate of oxide is higher than the etching rate of nitride. When the oxide layer contacts with the ending point which is situated between the oxide layer and the nitride layer or the nitride oxide layer, the etching rate of nitride is higher than the etching rate of oxide to form the flatter surface of the electrically insulating layer.

Abstract: A method for fabricating a NROM is described, in which a bottom anti-reflective coating (BARC) and a photoresist pattern are sequentially formed on a substrate that has a charge trapping layer formed thereon. An etching process is then performed to pattern the BARC and the charge trapping layer with the photoresist pattern as a mask. The etching process is conducted in an etching chamber equipped with a source power supply and a bias power supply, which two have a power ratio of 1.5˜3, while an etchant used therein is a gas plasma containing trifluoromethane (CHF3) and tetrafluoromethane (CF4). Thereafter, a buried drain is formed in the substrate, a buried drain oxide layer is formed on the buried drain, and then plural gates are formed on the substrate.

Abstract: A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.

Abstract: A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides.

Abstract: A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.

Abstract: A method for fabricating shallow trench isolation structures. A substrate is provided on which are sequentially stacked a buffer oxide layer and a mask layer. A plurality of trenches with different densities is formed in the stack of substrate/buffer oxide/mask layers. An insulating layer is formed over the substrate to fill the trenches. A planarized sacrificial layer is formed by spin coating polymer on the insulating layer. The sacrificial layer is completely removed by dry etching. A predetermined thickness of the insulating layer is removed such that a preliminary planarization of the insulating layer is obtained. By adjusting the etching parameters, the insulating layer is continuously removed by dry etching until the mask layer is exposed. The mask layer and buffer oxide layer are sequentially removed to expose a plurality of isolation structures with rounded surfaces.

Abstract: This invention relates to a method for fabricating a electrically insulating layer, more particularly, to the method for fabricating a electrically insulating layer by using the different etching rates in etching oxide and etching nitride. The present invention uses the way in different etching rates to etch oxide and nitride. When begin the etching process to fabricating the electrically insulating layer, the etching rate of oxide is higher than the etching rate of nitride. When the oxide layer contacts with the ending point which is situated between the oxide layer and the nitride layer or the nitride oxide layer, the etching rate of nitride is higher than the etching rate of oxide to form the flatter surface of the electrically insulating layer.

Abstract: The present invention provides an effective rapid thermal annealing process to fill a narrow contact window and to interconnect two conductive layers in semiconductor devices. The present invention rapidly raises an annealing temperature by a simple step of temperature raising under pure nitrogen after a step of depositing a contact layer and a barrier layer and before a step of filling a conductive layer in the contact window. Therefore, ammonia, which requires disposal treatment, is avoided and a good interconnection can be accomplished at a relative low temperature without damaging the conductive layers.

Abstract: A method and apparatus for improving the accuracy of laser ranging finding. The time difference obtained from laser range finding is converted into a voltage signal by a linear charge circuit with constant current and then digitized into a digital value by an analog to digital converter. A self calibration method is used to compensate for the thermal effect in a user's environment and improve the precision of the distance measurement obtained from the laser range finder. The self calibration method includes measuring two voltage values by using two correction pulses with known width after the laser range finder is initialized. The standard values in response to the two correction pulses are used to calibrate the measured data for obtaining a correction gain and a correction level. An instant distance value measured from a target can be calibrated by the correction gain and level to achieve higher precision of range finding.

Abstract: A method and apparatus for reducing the noise of a laser range finder. The laser range finder includes a high voltage silent circuit, a logarithmic amplifier and a sun noise averaging amplifier. The high voltage silent circuit shuts down the switched power supply controller of the high voltage power supply to reduce the noise coupled from the high voltage power supply when the receiver of the laser range finder is in a receiving mode. The logarithmic amplifier provides dynamic gain control for the receiver to avoid signal saturation and improve the signal to noise ratio of the received signal. The sun noise averaging amplifier provides an amplified average sun noise which automatically adjusts the threshold voltage of detecting the distance signal from a target.