Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A method of forming a semiconductor device, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

Abstract: A method includes performing a cleaning process on a first surface of a first wafer, and performing a surface activation process on the first surface. The surface activation process is selected from the group consisting of: a plasma surface activation process comprising generating a plasma from a process gas, wherein ions in the plasma are removed using a filter, and wherein a remaining uncharged part of the plasma is used to treat the first surface; a laser surface activation process using a laser beam; an acid surface activation process using an acid; and an alkali surface activation process using an alkali. After the surface activation process, a rinsing process is performed on the first surface. The first surface of the first wafer is bonded to a second surface of a second wafer.

Abstract: Examples include a computing system having a direct memory access (DMA) engine pipeline, a plurality of processing cores, each processing core including a core pipeline, and a memory coupled to the DMA engine pipeline and the plurality of processing cores. The computing system includes a pipeline selector coupled to the plurality of processing cores and the DMA engine pipeline, the pipeline selector to, during initialization, determine at least one threshold for pipeline selection for the computing system, and during runtime, select one of the core pipelines or the DMA engine pipeline to execute a memory copy operation in the memory based at least in part on the at least one threshold.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

Abstract: The present technology improves points-of-interest (POIs) in applications by the gathering and use of data available from various sources to improve metadata of POIs in applications (e.g., map applications) or any other metadata or information that may be of interest to a user regarding any given POI. The present technology resolves transactions to POIs or Brands (in a map application, for example) and improves, updates, creates, and removes POls/Brands. The present technology can also gain a clear name, granular and correct categorization, a URL, phone/chat contact info, etc. of the transactions.

Abstract: An electric valve, comprising a housing and an end cover. A cavity and a valve port are formed in the housing. The electric valve further comprises a rotor assembly, a rod assembly, and a valve core assembly; the rotor assembly is connected to one end of the rod assembly; and the other end of the rod assembly is connected to the valve core assembly. The electric valve further comprises a sealing component, and the sealing component is distant from the valve port with respect to the valve core assembly; the sealing component comprises a first cylindrical portion, a membrane portion, and an annular sealing portion; by providing the sealing component, the first cylindrical portion is connected to the rod assembly and a connection position is sealed.

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.

Abstract: A method for calibrating a micro-electro-mechanical system (MEMS) gyroscopes by determining a plurality of variates including quadrature and inphase values from output data of a first subset of the MEMS gyroscopes, determining offset temperature coefficients of the first subset of the MEMS gyroscopes over temperature variation, computing a linear regression using the quadrature and inphase values and the offset temperature coefficients to determine linear regression variate coefficients for predicting the offset temperature coefficient based on the quadrature and inphase values.

Abstract: Methods and apparatus relating to a universal core to accelerator communication architecture for enhanced performance and/or programmability are described. In an embodiment, a sending agent is coupled to a processor core and a receiving agent is coupled to a hardware accelerator device. Memory store data corresponding to a request from the processor core. The sending agent and the receiving agent maintain a communication channel to facilitate communication between the processor core and the hardware accelerator device in response to the request. Other embodiments are also disclosed and claimed.

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Abstract: A layer stack is formed over a conductive material portion located on a substrate. The layer stack contains a first silicon oxide layer, a silicon nitride layer formed by chemical vapor deposition, and a second silicon oxide layer. A patterned etch mask layer including an opening is formed over the layer stack. A via cavity extending through the layer stack and down to the conductive material portion is formed by isotropically etching portions of the layer stack underlying the opening in the patterned etch mask layer using an isotropic etch process. A buffered oxide etch process may be used, in which the etch rate of the silicon nitride layer is less than, but is significant enough, compared to the etch rate of the first silicon oxide layer to provide tapered straight sidewalls on the silicon nitride layer. An optical device including a patterned layer stack can be provided.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.

Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: An electronic device includes a display and a sensor underneath the display. The display has a full pixel density region and a reduced pixel density region. Compared to pixels in the full pixel density region, pixels in the reduced pixel density region can be controlled using overdriven power supply voltages, overdriven scan control signals, different initialization and reset voltages, and can include capacitors and transistors with different physical and electrical characteristics. Gate drivers provide scan signals to pixels in the full pixel density region, whereas overdrive buffers provide overdrive scan signals to pixels in the reduced pixel density region. The pixels in the full pixel density region and the pixels in the reduced pixel density region can be controlled using different black level or gamma settings for each color channel and can be adjusted physically to match luminance, color, as well as to mitigate differences in temperature and aging impact.

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.