Patents by Inventor Ren Wang

Ren Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200176327
    Abstract: A method of manufacturing a semiconductor device includes implanting a channel region of a first transistor and a channel region of a second transistor to have a first conductivity type. The method further includes forming source/drain regions of the first transistor to have the first conductivity type and source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type. The method further includes depositing a first work function layer over the channel region of the first transistor. The method further includes depositing a second work function layer over the channel region of the second transistor, wherein the first work function layer includes a same material as the second work function layer.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Inventors: Jhong-Sheng WANG, Ting-Sheng HUANG, Jiaw-Ren SHIH
  • Publication number: 20200176331
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200173051
    Abstract: An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.
    Type: Application
    Filed: November 7, 2019
    Publication date: June 4, 2020
    Inventors: Jun-Nan Nian, Shiu-Ko JANGJIAN, Ting-Chun WANG, Ing-Ju LEE, Yu-Ren PENG, Yao-Hsiang LIANG
  • Publication number: 20200176310
    Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 4, 2020
    Inventors: Jun-Nan Nian, Shiu-Ko JANGJIAN, Yu-Ren PENG, Yao-Hsiang LIANG, Ting-Chun WANG
  • Patent number: 10662326
    Abstract: A process for producing a flame-retardant polyester includes step (a) and step (b). In step (a), a combination of a bis-hydroxy alkyl terephthalate monomer and an organic diacid monomer mixture which includes an aromatic dicarboxylic acid monomer and a carboxy-phosphinic acid monomer is subjected to an esterification reaction to form an esterification reaction product. In step (b), the esterification reaction product is subjected to a polycondensation reaction.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Far Easter New Century Corporation
    Inventors: Der-Ren Hwang, Cheng-Ting Wang, Yen-Hsien Li
  • Publication number: 20200156108
    Abstract: A voltage burst is generated using a voltage supply having a single DC output voltage, VH coupled with a switching arrangement, including an input and a voltage transmitter output (Tx_Out), the input coupled with the output of the voltage supply. A control arrangement coupled with the switching arrangement is configured to operate the switching arrangement so as to provide, at the Tx_Out, a voltage burst that varies between an intermediate voltage, VM, and one or both of VH, and a minimum voltage, VL, where VL<VM<VH.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Shitong Zhao, Masoud Roham, Lennart Mathe, Bo-Ren Wang
  • Patent number: 10651174
    Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 12, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 10647700
    Abstract: An inhibitor of a wild type and Y641F mutant of human histone methyltransferase EZH2 is provided herein. Particularly, the inhibitor is a compound represented by formula (I) or a pharmaceutically acceptable salt thereof. The inhibitor can be used to treat a cancer or precancerous condition related to EZH2 activity.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: May 12, 2020
    Assignee: TARAPEUTICS SCIENCE INC.
    Inventors: Qingsong Liu, Jing Liu, Fengchao Lv, Chen Hu, Wen Liang Wang, Ao Li Wang, Zi Ping Qi, Xiao Fei Liang, Wen Chao Wang, Tao Ren, Bei Lei Wang, Li Wang
  • Publication number: 20200144102
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
  • Patent number: 10641526
    Abstract: A cooling apparatus includes a container configured to contain a coolant within a space. The apparatus further includes a cooling block positioned substantially within the space and having a high heat capacity such that the space not occupied by the cooling block is filled with a coolant to a level at or below the top of the cooling block, and a placement structure having high thermal conductivity positioned on top of the cooling block and outside of the space. A method for cooling an object is also provided, which includes inserting a coolant into a container configured to contain the coolant within a space, and placing the object on a placement structure outside the space. For this method, the placement structure has a high thermal conductivity and is coupled to a cooling block, the cooling block having a high heat capacity and positioned substantially within the space. A two-stage cooling apparatus and method is also described.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 5, 2020
    Assignee: GEMOLOGIAL INSTITUTE OF AMERICA, INC. (GIA)
    Inventors: Matt Hall, Ren Lu, Wuyi Wang
  • Publication number: 20200135922
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 30, 2020
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Chun-Wei Yu, Yu-Ren Wang
  • Publication number: 20200131308
    Abstract: A method for manufacturing polyester comprises mixing Bis(2-Hydroxyethyl) terephthalate monomer with terephthalic acid to form a mixture, in which the Bis(2-Hydroxyethyl) terephthalate monomer is represented by formula (I) below: esterifying the mixture to form a first polyester mixture; and polymerizing the first polyester mixture to form a second polyester mixture, in which the second polyester mixture has a diethylene glycol concentration of less than 1 wt % but greater than 0.1 wt %, based on the total weight of the second polyester mixture, and a polydispersity index of polyethylene terephthalate in the second polyester mixture is less than 3 but greater than 2.
    Type: Application
    Filed: April 25, 2019
    Publication date: April 30, 2020
    Inventors: Der-Ren HWANG, Cheng-Ting WANG, Hsiao-Chan WANG, Yi-Chen LEE
  • Patent number: 10635590
    Abstract: Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Ren Wang, Joseph Nuzman, Samantika S. Sury, Andrew J. Herdrich, Namakkal N. Venkatesan, Anil Vasudevan, Tsung-Yuan C. Tai, Niall D. McDonnell
  • Patent number: 10622481
    Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Hao-Hsuan Chang, Chia-Wei Hsu
  • Patent number: 10623311
    Abstract: Technologies for distributed table lookup via a distributed router includes an ingress computing node, an intermediate computing node, and an egress computing node. Each computing node of the distributed router includes a forwarding table to store a different set of network routing entries obtained from a routing table of the distributed router. The ingress computing node generates a hash key based on the destination address included in a received network packet. The hash key identifies the intermediate computing node of the distributed router that stores the forwarding table that includes a network routing entry corresponding to the destination address. The ingress computing node forwards the received network packet to the intermediate computing node for routing. The intermediate computing node receives the forwarded network packet, determines a destination address of the network packet, and determines the egress computing node for transmission of the network packet from the distributed router.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Sameh Gobriel, Ren Wang, Christian Maciocco, Tsung-Yuan Tai
  • Publication number: 20200104259
    Abstract: A snapshot prefetcher to perform snapshot prefetching to improve performance of snapshot read operations. An apparatus embodiment includes a snapshot read tracking circuitry to track snapshot read requests made by a first processor core to read a plurality of cache lines, and to detect a snapshot read access stream based on the tracked snapshot read requests. A snapshot prefetch issuing circuitry of the apparatus to issue, based on the detected snapshot read access stream, one or more snapshot prefetch requests, including a first snapshot prefetch request to prefetch data from a first cache line stored in, and owned exclusively by, a first storage location outside the first processor core. The snapshot prefetch issuing circuitry further to store the prefetched data in a second storage location within the first processor core, wherein after the prefetch, exclusive ownership of the first cache line is to remain with the first storage location.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Ren Wang, Lawrence C. Stewart, Binh Pham, Andrew Herdrich, Venkata Krishnan, Anil Vasudevan, Joseph Nuzman, Tsung-Yuan Tai
  • Publication number: 20200106867
    Abstract: One embodiment provides a network system. The network system includes an application layer to execute one or more networking applications to generate or receive data packets having flow identification (ID) information; and a packet processing layer having profiling circuitry to generate a sketch table indicative of packet flow count data; the sketch table having a plurality of buckets, each bucket includes a first section including a plurality of data fields, each data field of the first section to store flow ID and packet count data, each bucket also having a second section having a plurality of data fields, each data field of the second section to store packet count data.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Ren Wang, Yipeng Wang, Tsung-Yuan Tai
  • Patent number: 10606755
    Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship, Vedaraman Geetha, Shrikant M. Shah, Marshall A. Millier, Raanan Sade, Binh Q. Pham, Olivier Serres, Chyi-Chang Miao, Christopher B. Wilkerson
  • Patent number: 10607897
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200098916
    Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.
    Type: Application
    Filed: October 28, 2018
    Publication date: March 26, 2020
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang