Patents by Inventor Ren Wang

Ren Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12608243
    Abstract: A network interface card (NIC) can be configured to monitor a first central processing unit (CPU) core mapped to a first receive queue having a receive queue length. The NIC can also be configured to determine whether the CPU core is overloaded based on the receive queue length. The NIC can also be configured to redirect data packets that were targeted from the first receive queue to the CPU core to another CPU core responsive to a determination that the CPU core is overloaded.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: April 21, 2026
    Assignee: Intel Corporation
    Inventors: Ren Wang, Daniel P. Daly, Antoine Kaufmann, Saikrishna Edupuganti, Tsung-Yuan C. Tai
  • Publication number: 20260097360
    Abstract: A method and a system for collaborative prediction and intelligent control of multiple pollutants in waste incineration flue gas are provided. The method includes: constructing a multi-pollutant collaborative prediction model for four types of flue gas pollutants in waste incineration flue gas based on a deep learning algorithm; constructing a cost index function considering an absorbent dosage and an environmental protection index function considering pollutant emission amounts by integrating multi-objective optimization methods; determining optimal dosage data of absorbents corresponding to the four types of flue gas pollutants; controlling and adjusting an opening degree of the dispensing valve of the each absorbent based on the optimal dosage data, thereby achieving intelligent control of multiple pollutants in waste incineration flue gas.
    Type: Application
    Filed: September 30, 2025
    Publication date: April 9, 2026
    Applicant: ZHEJIANG UNIVERSITY
    Inventors: Xiaoqing LIN, Ren WANG, Jie CHEN, Qunxing HUANG, Xiaodong LI, Jianhua YAN
  • Patent number: 12596679
    Abstract: Methods, apparatus, systems, and articles of manufacture providing a tiered elastic cloud storage to increase data resiliency are disclosed. An example instructions cause one or more processors to at least execute the instructions to: generate a storage scheme for files based on a categorization of the files and resource capabilities of an edge-based device and a cloud-based device, the categorization including a first group of files to be stored locally at an end user computing device, a second group of files to be stored externally at the edge-based device, and a third group of files to be stored externally at the cloud-based device; in response to an acknowledgement from at least one of the edge-based device or the cloud-based device, generate a map corresponding to locations of the files; store the first group of files in local storage; and cause transmission of the second group of files to the edge-based device and the third group of files to the cloud-based device.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 7, 2026
    Assignee: Intel Corporation
    Inventors: Ren Wang, Christian Maciocco, Kshitij Doshi, Francesc Guim Bernat, Ned Smith, Satish Jha, Vesh Raj Sharma Banjade, S M Iftekharul Alam
  • Publication number: 20260078647
    Abstract: The present invention relates to the field of drilling coring devices. Disclosed are a pressure-preserved coring tool, a use method, and a reservoir analysis method. The pressure-preserved coring tool comprises an outer cylinder (1), a differential assembly (2), a pressure-preserving inner cylinder assembly (4), and a seal assembly (5). The differential assembly is configured to be able to drive the pressure-pre-serving inner cylinder assembly to move upwards relative to the seal assembly, so that the seal assembly seals the inner cylinder assembly for accommodating a rock core (8).
    Type: Application
    Filed: September 8, 2023
    Publication date: March 19, 2026
    Inventors: Yang SU, Shaoliang SUN, Ren WANG, Jun LUO, Shangwen ZHOU, Mengyu XIE, Boyi XIA, Xianggang DUAN, Yang JIAO, Liang TANG, Chenchen DONG, Li WEN
  • Publication number: 20260010402
    Abstract: Examples described herein relate to a work scheduler that includes at least one processor and at least one queue. In some examples, the work scheduler receives a request to allocate a region of memory and based on availability of a memory segment associated with a central cache to satisfy the request to allocate a region of memory, provide a memory allocation using an available memory segment entry associated with the central cache from the at least one queue. In some examples, the work scheduler assigns a workload to a processor and controls when to pre-fetch content relevant to the workload to store in a cache or memory accessible to the processor based on a position of the workload in a work queue associated with the processor.
    Type: Application
    Filed: September 15, 2025
    Publication date: January 8, 2026
    Inventors: Yipeng WANG, Ren WANG, Tsung-Yuan C. TAI, Yifan YUAN, Pravin PATHAK, Sundar VEDANTHAM, Chris MACNAMARA
  • Patent number: 12498974
    Abstract: Methods, apparatus, and systems for adaptive collaborative memory with the assistance of programmable networking devices. Under one example, the programmable networking device is a switch that is deployed in a system or cluster of servers comprising a plurality of nodes. The switch selects one or more nodes to be remote memory server nodes and allocate one or more portions of memory on those nodes to be used as remote memory for one or more remote memory client nodes. The switch receives memory access request messages originating from remote memory client nodes containing indicia identifying memory to be accessed, determines which remote memory server node is to be used for servicing a given memory access request, and sends a memory access request message containing indicia identifying memory to be accessed to the remote memory server node that is determined. The switch also facilitates return of messages containing remote memory access responses to the client nodes.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: December 16, 2025
    Assignee: Intel Corporation
    Inventors: Ren Wang, Christian Maciocco, Yipeng Wang, Kshitij A. Doshi, Vesh Raj Sharma Banjade, Satish C. Jha, S M Iftekharul Alam, Srikathyayani Srikanteswara, Alexander Bachmutsky
  • Publication number: 20250377881
    Abstract: The present disclosure relates to a method, device, and computer program product for updating an application programming interface (API). The method includes identifying a code segment of a first version from the API. The method further includes converting the code segment of the first version to a first abstract syntax tree (AST) according to a first conversion strategy. The method further includes generating a second AST according to the first AST. The method further includes converting the second AST to a code segment of a second version according to a second conversion strategy. In scenarios where an API is automatically updated, the method according to the present disclosure can improve the accuracy of updating the API, thereby improving the efficiency of updating.
    Type: Application
    Filed: July 30, 2024
    Publication date: December 11, 2025
    Inventors: Lian LI, Ren WANG, Cheng YANG, Yuhong NIE, Weiyang LIU, Yun ZHANG
  • Patent number: 12484594
    Abstract: A method for extending shelf life of germ remained rice includes evenly spreading the germ remained rice on a sheet tray, and moderately moistening the germ remained rice, packing the germ remained rice moistened, and irradiating the germ remained rice with an electron beam.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: December 2, 2025
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Ren Wang, Yudan Jin, Haibo Li, Wei Feng, Tao Wang, Hao Zhang
  • Patent number: 12448634
    Abstract: A method for preparing V-type granular porous starch includes the following steps: mixing starch and an ethanol aqueous solution in a temperature of 100-150° C. to yield V-type granular starch; and adding a mixed enzyme including alpha-amylase and amyloglucosidase to a mixture of the V-type granular starch and the ethanol aqueous solution, to enzymatically hydrolyze the V-type granular starch to yield V-type granular porous starch.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: October 21, 2025
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Xing Zhou, Zhengyu Jin, Qing Chang, Ren Wang, Jinpeng Wang, Jianwei Zhao, Aiquan Jiao, Jie Long
  • Patent number: 12443443
    Abstract: Examples described herein relate to a work scheduler that includes at least one processor and at least one queue. In some examples, the work scheduler receives a request to allocate a region of memory and based on availability of a memory segment associated with a central cache to satisfy the request to allocate a region of memory, provide a memory allocation using an available memory segment entry associated with the central cache from the at least one queue. In some examples, the work scheduler assigns a workload to a processor and controls when to pre-fetch content relevant to the workload to store in a cache or memory accessible to the processor based on a position of the workload in a work queue associated with the processor.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: October 14, 2025
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Yipeng Wang, Ren Wang, Tsung-Yuan C. Tai, Yifan Yuan, Pravin Pathak, Sundar Vedantham, Chris MacNamara
  • Patent number: 12418498
    Abstract: Technologies for dynamically managing a batch size of packets include a network device. The network device is to receive, into a queue, packets from a remote node to be processed by the network device, determine a throughput provided by the network device while the packets are processed, determine whether the determined throughput satisfies a predefined condition, and adjust a batch size of packets in response to a determination that the determined throughput satisfies a predefined condition. The batch size is indicative of a threshold number of queued packets required to be present in the queue before the queued packets in the queue can be processed by the network device.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: September 16, 2025
    Assignee: Intel Corporation
    Inventors: Ren Wang, Mia Primorac, Tsung-Yuan C. Tai, Saikrishna Edupuganti, John J. Browne
  • Publication number: 20250279972
    Abstract: Technologies for dynamically managing a batch size of packets include a network device. The network device is to receive, into a queue, packets from a remote node to be processed by the network device, determine a throughput provided by the network device while the packets are processed, determine whether the determined throughput satisfies a predefined condition, and adjust a batch size of packets in response to a determination that the determined throughput satisfies a predefined condition. The batch size is indicative of a threshold number of queued packets required to be present in the queue before the queued packets in the queue can be processed by the network device.
    Type: Application
    Filed: April 30, 2025
    Publication date: September 4, 2025
    Applicant: Intel Corporation
    Inventors: Ren Wang, Mia Primorac, Tsung-Yuan C. Tai, Saikrishna Edupuganti, John J. Browne
  • Publication number: 20250265125
    Abstract: Examples described herein relate to circuitry to select a first load balancer from among multiple load balancers to allocate a packet to a processor core among multiple processor cores of a processor and change from the first load balancer to select a second load balancer among the multiple load balancers based on a change in load metrics. In some examples, the multiple load balancers include at least: a load balancer that selects a processor core among the multiple processor cores based on a hash calculation on packet content and a load balancer that load balances among the multiple processor cores based on the load metrics.
    Type: Application
    Filed: April 14, 2025
    Publication date: August 21, 2025
    Inventors: Jiaqi LOU, Ren WANG
  • Patent number: 12373363
    Abstract: Examples include a computing system having a direct memory access (DMA) engine pipeline, a plurality of processing cores, each processing core including a core pipeline, and a memory coupled to the DMA engine pipeline and the plurality of processing cores. The computing system includes a pipeline selector coupled to the plurality of processing cores and the DMA engine pipeline, the pipeline selector to, during initialization, determine at least one threshold for pipeline selection for the computing system, and during runtime, select one of the core pipelines or the DMA engine pipeline to execute a memory copy operation in the memory based at least in part on the at least one threshold.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 29, 2025
    Assignee: Intel Corporation
    Inventors: Jiayu Hu, Ren Wang, Cunming Liang
  • Patent number: 12359935
    Abstract: The present technology improves points-of-interest (POIs) in applications by the gathering and use of data available from various sources to improve metadata of POIs in applications (e.g., map applications) or any other metadata or information that may be of interest to a user regarding any given POI. The present technology resolves transactions to POIs or Brands (in a map application, for example) and improves, updates, creates, and removes POls/Brands. The present technology can also gain a clear name, granular and correct categorization, a URL, phone/chat contact info, etc. of the transactions.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: July 15, 2025
    Assignee: Apple Inc.
    Inventors: Shanni A. Weilert, Ryan Studelska, Ren Wang, Ievgeniia Gutenko, Fang Ji, Andrei Makhanov, Aditya Rane, Jarad M. Fisher, Akila Suresh, Ashish C. Nagre, Andrew Williams, Victor Shugaev
  • Patent number: 12352358
    Abstract: An electric valve, comprising a housing and an end cover. A cavity and a valve port are formed in the housing. The electric valve further comprises a rotor assembly, a rod assembly, and a valve core assembly; the rotor assembly is connected to one end of the rod assembly; and the other end of the rod assembly is connected to the valve core assembly. The electric valve further comprises a sealing component, and the sealing component is distant from the valve port with respect to the valve core assembly; the sealing component comprises a first cylindrical portion, a membrane portion, and an annular sealing portion; by providing the sealing component, the first cylindrical portion is connected to the rod assembly and a connection position is sealed.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: July 8, 2025
    Assignee: ZHEJIANG SANHUA AUTOMOTIVE COMPONENTS CO., LTD.
    Inventors: Ren Wang, Lixin Wang
  • Patent number: 12339136
    Abstract: A method for calibrating a micro-electro-mechanical system (MEMS) gyroscopes by determining a plurality of variates including quadrature and inphase values from output data of a first subset of the MEMS gyroscopes, determining offset temperature coefficients of the first subset of the MEMS gyroscopes over temperature variation, computing a linear regression using the quadrature and inphase values and the offset temperature coefficients to determine linear regression variate coefficients for predicting the offset temperature coefficient based on the quadrature and inphase values.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: June 24, 2025
    Assignee: InvenSense, Inc.
    Inventors: Zhongzheng Liu, Jongwoo Shin, Ren Wang
  • Publication number: 20250199890
    Abstract: Methods and apparatus relating to a universal core to accelerator communication architecture for enhanced performance and/or programmability are described. In an embodiment, a sending agent is coupled to a processor core and a receiving agent is coupled to a hardware accelerator device. Memory store data corresponding to a request from the processor core. The sending agent and the receiving agent maintain a communication channel to facilitate communication between the processor core and the hardware accelerator device in response to the request. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 15, 2022
    Publication date: June 19, 2025
    Applicant: Intel Corporation
    Inventors: Yipeng Wang, Rajesh M. Sankaran, Ren Wang, Narayan Ranganathan, Jr-Shian Tsai, Tsung-Yuan Tai, Heqing Zhu, Ilia Kurakin, Binh Pham, Halit Dogan
  • Patent number: 12293231
    Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Chenmin Sun, Yipeng Wang, Rahul R. Shah, Ren Wang, Sameh Gobriel, Hongjun Ni, Mrittika Ganguli, Edwin Verplanke
  • Publication number: 20250110755
    Abstract: A method for providing an interface includes acquiring a general interface specification associated with a back-end interface. The method further includes generating, based on the general interface specification and a first mapping, a first front-end interface specification. The method further includes converting, based on the first front-end interface specification, a first front-end request into a first back-end request associated with the back-end interface. The method further includes generating, based on the general interface specification and a second mapping, a second front-end interface specification, the second mapping indicating a relationship between the general interface specification and the second front-end interface specification. Furthermore, the method further includes converting, based on the second front-end interface specification, a second front-end request into a second back-end request associated with the back-end interface.
    Type: Application
    Filed: November 9, 2023
    Publication date: April 3, 2025
    Inventors: Yuefeng Li, Ren Wang, Yun Zhang, Weiyang Liu, Qi Wang