Abstract: A nanographene, a preparation method thereof, and uses thereof are disclosed. The method of preparing the nanographene includes the steps: (1) carrying out a first reaction by contacting a raw material graphite and a first oxidizing agent with an intercalating agent to obtain a modified graphite; (2) performing a second reaction by contacting the modified graphite and an acid with a second oxidizing agent to obtain a graphene pre-product; and (3) subjecting the graphene pre-product to an air-flow exfoliation to prepare a nanographene. An oil-based drilling fluid containing the nanographene produced by the method is also disclosed.

Abstract: A method for batching pages for a data movement accelerator of a processor. The method includes determining a plurality of memory regions having a similar content according to a similarity criterion, wherein each memory region comprises a plurality of pages. The method further includes determining a plurality of page groups, wherein each page group comprises a plurality of counterpart pages between the plurality of memory regions. The method then includes providing the plurality of page groups to the data movement accelerator for parallel processing.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

Abstract: The present technology improves points-of-interest (POIs) in applications by the gathering and use of data available from various sources to improve metadata of POIs in applications (e.g., map applications) or any other metadata or information that may be of interest to a user regarding any given POI. The present technology resolves transactions to POIs or Brands (in a map application, for example) and improves, updates, creates, and removes POls/Brands. The present technology can also gain a clear name, granular and correct categorization, a URL, phone/chat contact info, etc. of the transactions.

Abstract: A semiconductor device and a method are provided. The semiconductor device includes gate structures extending on a substrate along a first direction and arranged in a second direction in parallel with one another, source and drain regions disposed in the substrate between the parallel gate structures, and dielectric structures disposed on the substrate and between the gate structures. The semiconductor device further includes an ILD layer disposed over the gate structures and the dielectric structures, contact structures disposed beside and between the parallel gate structures and separators embedded in the ILD layer. Each contact structure extends vertically through the ILD layer and the dielectric structures, and the separators are disposed above the gate structures and disposed beside the contact structures.

Abstract: A nanographene, a preparation method thereof, and uses thereof are disclosed. The method of preparing the nanographene includes the steps: (1) carrying out a first reaction by contacting a raw material graphite and a first oxidizing agent with an intercalating agent to obtain a modified graphite; (2) performing a second reaction by contacting the modified graphite and an acid with a second oxidizing agent to obtain a graphene pre-product; and (3) subjecting the graphene pre-product to an air-flow exfoliation to prepare a nanographene. An oil-based drilling fluid containing the nanographene produced by the method is also disclosed.

Abstract: A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

Abstract: A display panel includes a substrate composed of a plurality of pixels; and a plurality of integrated circuits (ICs) disposed on a top surface of the substrate, each IC including a plurality of IC pads and the substrate including a plurality of substrate pads corresponding to the IC pads and disposed on the top surface of the substrate. In one embodiment, the ICs are bonded on the substrate via the IC pads and the substrate pads, which are interconnected by laser as a heat source. In another embodiment, each IC is disposed above to cover up at least one pixel.

Abstract: Methods and apparatus for efficiently merging non-identical pages in Kernel Same-page Merging (KSM) for efficient and improved memory deduplication and security. The methods and apparatus identify memory pages with similar data and selectively merge those pages based on criteria such as a threshold. Memory pages in memory for a computing platform are scanned to identify pages storing similar but not identical data. A delta record between the similar memory pages is created, and it is determined whether a size of the delta (i.e., amount of content that is different) is less than a threshold. If so, the delta record is used to merge the pages. In one aspect, operations for creating delta records and merging the content of memory pages using delta records is offloaded from a platform's CPU. Support for memory reads and memory writes are provided utilizing delta records, including merging and unmerging pages under applicable conditions.

Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

Abstract: An electrical connector includes: an insulating body; plural conductive terminals disposed in the insulating body, the conductive terminals including two signal terminals and one ground terminal arranged between the two signal terminals; a cable connected with the conductive terminals; and a metal shell disposed outside the insulating body, the metal shell including a top wall, an opening being set on the top wall, the shape of the opening being rectangular, the top wall being provided with elastic pieces protruding inward from the opening to electrically connect with the ground terminal, wherein the opening is sized and configured to achieve better electrical performance of the conductive terminals.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.

Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.

Abstract: Technologies for dynamically managing a batch size of packets include a network device. The network device is to receive, into a queue, packets from a remote node to be processed by the network device, determine a throughput provided by the network device while the packets are processed, determine whether the determined throughput satisfies a predefined condition, and adjust a batch size of packets in response to a determination that the determined throughput satisfies a predefined condition. The batch size is indicative of a threshold number of queued packets required to be present in the queue before the queued packets in the queue can be processed by the network device.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes separating an interlayer dielectric (ILD) into a plurality of portions. The plurality of portions of ILD, separated from each other along a first lateral direction and a second lateral direction, overlay a plurality of groups of epitaxial regions, respectively. The method includes performing an etching process to expose the plurality of groups of epitaxial regions, wherein the etching process comprises a plurality of stages, each of the stages comprising a respective etchant. The method includes forming a plurality of conductive contacts electrically coupled to the plurality of epitaxial regions, respectively.