Patents by Inventor Ren Wang
Ren Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12210434Abstract: An apparatus and method for closed loop dynamic resource allocation.Type: GrantFiled: June 27, 2020Date of Patent: January 28, 2025Assignee: Intel CorporationInventors: Bin Li, Ren Wang, Kshitij Arun Doshi, Francesc Guim Bernat, Yipeng Wang, Ravishankar Iyer, Andrew Herdrich, Tsung-Yuan Tai, Zhu Zhou, Rasika Subramanian
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Patent number: 12205905Abstract: A semiconductor structure includes a substrate including a device region, a peripheral region surrounding the device region, and a transition region disposed between the device region and the peripheral region. An epitaxial layer is disposed on the device region, the peripheral region, and the transition region. A first portion of the epitaxial layer on the peripheral region has a poly-crystal structure.Type: GrantFiled: February 19, 2021Date of Patent: January 21, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
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Patent number: 12197601Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.Type: GrantFiled: December 22, 2021Date of Patent: January 14, 2025Assignee: Intel CorporationInventors: Ren Wang, Sameh Gobriel, Somnath Paul, Yipeng Wang, Priya Autee, Abhirupa Layek, Shaman Narayana, Edwin Verplanke, Mrittika Ganguli, Jr-Shian Tsai, Anton Sorokin, Suvadeep Banerjee, Abhijit Davare, Desmond Kirkpatrick, Rajesh M. Sankaran, Jaykant B. Timbadiya, Sriram Kabisthalam Muthukumar, Narayan Ranganathan, Nalini Murari, Brinda Ganesh, Nilesh Jain
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Publication number: 20250014948Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.Type: ApplicationFiled: September 15, 2024Publication date: January 9, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
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Patent number: 12185655Abstract: A method for micro-ridge mixed-sowing cultivation of dryland crops includes the following steps: S1: cleaning ditches and draining away water in dryland; S2: harvesting the preceding crop, leaving the stubble, smashing the stalks of the preceding crop, and then spreading the smashed stalks on the stubble; S3: trenching the dryland to form ecological trenches; S4: flattening the standing stubble and the smashed stalks on the seedbed surface to form an underlying surface, molding seed-fertilizer-soil compounds into a ridge shape and allowing the seed-fertilizer-soil compounds to fall on the underlying surface to form ecological ridges, wherein a plurality of ecological ridges are formed between adjacent ecological trenches, an ecological depression is formed between adjacent ecological ridges, and after sowing, an irrigation is carried out, including: draining water shortly after the irrigation, without leaving a water layer in the field.Type: GrantFiled: April 26, 2021Date of Patent: January 7, 2025Assignee: Hunan Agriculture UniversityInventors: Huang Huang, Yin Zhang, Jingyi Li, Ren Wang, Xiangsheng Gong, Zhiqiang Fu, Can Chen, Zhengjun Yu, Yugang Liang, Jiaolong Ding, Xiangjie Meng, Dan Wu, Yao Huang, Xiaolan Liao
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Patent number: 12185631Abstract: In some embodiments, the present disclosure relates to a piezomicroelectromechanical system (piezoMEMS) device that includes a second piezoelectric layer arranged over the first electrode layer. A second electrode layer is arranged over the second piezoelectric layer. A first contact is arranged over and extends through the second electrode layer and the second piezoelectric layer to contact the first electrode layer. A dielectric liner layer is arranged directly between the first contact and inner sidewalls of the second electrode layer and the second piezoelectric layer. A second contact is arranged over and electrically coupled to the second electrode layer, wherein the second contact is electrically isolated from the first contact.Type: GrantFiled: July 20, 2023Date of Patent: December 31, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Ren Wang, Hung-Hua Lin, Yuan-Chih Hsieh
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Patent number: 12174721Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product that involve exporting a log. The method includes acquiring a first set of attributes indicating a target asset among assets protected by a data protection product, a second set of attributes indicating target tasks executed on the target asset, and a third set of attributes indicating a computing resource running the data protection product. The method further includes determining an export time consumed to export a log of the target asset based on the first set of attributes, the second set of attributes, and the third set of attributes. With the embodiments of the present disclosure, the time required for exporting a log can be accurately estimated while the log is exported.Type: GrantFiled: April 26, 2022Date of Patent: December 24, 2024Assignee: DELL PRODUCTS L.P.Inventors: Huifeng Li, Ren Wang, Weiyang Liu, Jinjin Wang, Qi Wang, Yuefeng Li
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Publication number: 20240403107Abstract: Methods, apparatus, and computer programs are disclosed to schedule access to multiple accelerators. In one embodiment, a method is disclosed to perform: receiving a first request to process data for a first application by a first accelerator of a plurality of accelerators of a computing system, an accelerator of the plurality of accelerators being dedicated to one or more respective specialized computations of the computing system for data processing; scheduling resources for the first request based on the first request and a second request to process data for a second application by a second accelerator of the plurality of accelerators, the first and second requests having one or more priority indications indicating priority between the first and second requests; and processing the data for the first application using the resources as scheduled responsive to the first request.Type: ApplicationFiled: August 6, 2024Publication date: December 5, 2024Inventors: Ren WANG, Yifan YUAN
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Patent number: 12159930Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.Type: GrantFiled: August 29, 2022Date of Patent: December 3, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ming Hsu, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
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Publication number: 20240395556Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
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Patent number: 12151932Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.Type: GrantFiled: August 3, 2023Date of Patent: November 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
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Publication number: 20240387253Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Wei-Ren Wang, Jen Hung Wang, Tze-Liang Lee
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Publication number: 20240387268Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Inventors: Wei-Ren Wang, Jen Hung Wang, Tze-Liang Lee
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Patent number: 12148622Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.Type: GrantFiled: June 26, 2023Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
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Publication number: 20240379762Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
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Publication number: 20240368746Abstract: A microstructure may be provided by forming a metal layer such as a molybdenum layer over a substrate. An aluminum nitride layer is formed on a top surface of the metal layer. A surface portion of the aluminum nitride layer is converted into a continuous aluminum oxide-containing layer by oxidation. A dielectric spacer layer may be formed over the continuous aluminum oxide-containing layer. Contact via cavities extending through the dielectric spacer layer, the continuous aluminum oxide containing layer, and the aluminum nitride layer and down to a respective portion of the at least one metal layer may be formed using etch processes that contain a wet etch step while suppressing formation of an undercut in the aluminum nitride layer. Contact via structures may be formed in the contact via cavities. The microstructure may include a micro-electromechanical system (MEMS) device containing a piezoelectric transducer.Type: ApplicationFiled: July 21, 2024Publication date: November 7, 2024Inventors: Yuan-Chih Hsieh, Yi-Ren Wang, Hung-Hua Lin
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Publication number: 20240371645Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.Type: ApplicationFiled: July 18, 2024Publication date: November 7, 2024Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
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Patent number: 12134824Abstract: A microstructure may be provided by forming a metal layer such as a molybdenum layer over a substrate. An aluminum nitride layer is formed on a top surface of the metal layer. A surface portion of the aluminum nitride layer is converted into a continuous aluminum oxide-containing layer by oxidation. A dielectric spacer layer may be formed over the continuous aluminum oxide-containing layer. Contact via cavities extending through the dielectric spacer layer, the continuous aluminum oxide containing layer, and the aluminum nitride layer and down to a respective portion of the at least one metal layer may be formed using etch processes that contain a wet etch step while suppressing formation of an undercut in the aluminum nitride layer. Contact via structures may be formed in the contact via cavities. The microstructure may include a micro-electromechanical system (MEMS) device containing a piezoelectric transducer.Type: GrantFiled: June 17, 2022Date of Patent: November 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Chih Hsieh, Yi-Ren Wang, Hung-Hua Lin
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Patent number: 12125879Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.Type: GrantFiled: July 27, 2023Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
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Patent number: 12119272Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.Type: GrantFiled: August 14, 2023Date of Patent: October 15, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin