Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

Abstract: A method for preparing V-type porous starch includes: mixing starch and a first ethanol solution in a reaction kettle, adding concentrated hydrochloric acid to the reaction kettle for acidity regulation, and controlling a temperature of a reaction system in the reaction kettle at 80-150° C.; cooling the reaction kettle, and adding a sodium hydroxide solution to the reaction system in the reaction kettle, until a pH of a mixture in the reaction kettle is neutral, to yield a starch solution; and centrifuging the starch solution, washing a collected precipitate with a second ethanol solution, leaching, drying, cooling, and pulverizing, to yield V-type porous starch.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A depth estimation from focus method and system includes receiving input image data containing focus information, generating an intermediate attention map by an AI model, normalizing the intermediate attention map into a depth attention map via a normalization function, and deriving expected depth values for the input image data containing focus information from the depth attention map. The AI model for depth estimation can be trained unsupervisedly without ground truth depth maps. The AI model of some embodiments is a shared network estimating a depth map and reconstructing an AiF image from a set of images with different focus positions.

Abstract: The present invention relates to platform power management.

Abstract: An apparatus may include a sense resistor comprising a plurality of parallel-coupled resistor elements, a plurality of positive voltage sense points, and a plurality of negative voltage sense points. A first passive combination network may be configured to combine the plurality of positive voltage sense points into a single positive sense terminal and a second passive combination network may be configured to combine the plurality of negative voltage sense points into a single negative sense terminal. The first passive combination network and the second passive combination network may be arranged such that a sense voltage is measurable between the single positive sense terminal and the single negative sense terminal and a dependence of the sense voltage on a variation in current density in the parallel-coupled resistor elements is minimized.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A method for preparing protein nanoparticle microspheres includes: dispersing a protein powder in water, adjusting a pH of a solution of the protein powder to between 10.0 and 12.0, stirring, centrifuging, and collecting a first upper dispersion; adjusting the first upper dispersion to be neutral using a cation exchange resin, centrifuging, to yield a protein nanoparticle dispersion; adding eugenol to the protein nanoparticle dispersion, stirring, centrifuging, and removing a precipitant, to yield a core-shell nanoprotein dispersion comprising a eugenol core and a protein shell; and adding the core-shell nanoprotein dispersion to ultrapure water, dialyzing, centrifuging, collecting a second upper dispersion, freeze-drying the second upper dispersion, to yield protein nanoparticle microspheres.

Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for recommending a protection strategy. The method includes obtaining contents of attributes of a plurality of data assets adjusted. The method further includes generating a plurality of vector representations for the plurality of data assets based on the contents of the attributes. The method further includes dividing the plurality of data assets into at least one category based on the plurality of vector representations. The method further includes if it is determined that a protection strategy for one data asset in the at least one category exists, determining the protection strategy as a recommended strategy for another data asset in the at least one category.

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A method for enhancing a solubility of a plant protein includes: mixing a plant protein and water, and adjusting the pH value of a resulting mixture of the plant protein and water to 10-12 for dissolution of the plant protein, thereby obtaining a swollen plant protein; treating the swollen plant protein through ion exchange until the pH value of the mixture is 7-8, and filtering the mixture, to yield a first supernatant; separating the first supernatant to yield a second supernatant; and drying the second supernatant, to yield a modified plant protein whose solubility is higher than that of the raw plant protein.

Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.

Abstract: A nanographene, a preparation method thereof, and uses thereof are disclosed. The method of preparing the nanographene includes the steps: (1) carrying out a first reaction by contacting a raw material graphite and a first oxidizing agent with an intercalating agent to obtain a modified graphite; (2) performing a second reaction by contacting the modified graphite and an acid with a second oxidizing agent to obtain a graphene pre-product; and (3) subjecting the graphene pre-product to an air-flow exfoliation to prepare a nanographene. An oil-based drilling fluid containing the nanographene produced by the method is also disclosed.

Abstract: The present disclosure relates to the technical field of oilfield chemistry, and discloses an anti-sloughing drilling fluid and a use thereof.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

Abstract: A method for batching pages for a data movement accelerator of a processor. The method includes determining a plurality of memory regions having a similar content according to a similarity criterion, wherein each memory region comprises a plurality of pages. The method further includes determining a plurality of page groups, wherein each page group comprises a plurality of counterpart pages between the plurality of memory regions. The method then includes providing the plurality of page groups to the data movement accelerator for parallel processing.

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.