Abstract: Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

Abstract: A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of operating a memory device includes partitioning a memory array into a first portion of SLC blocks and a second portion of XLC blocks, storing at least a portion of host data into the first portion of SLC blocks as a static cache; and storing at least another portion of the host data into the second portion of XLC blocks in an SLC mode as a dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. Additional memory devices, methods, and computer systems are also described.

Abstract: Apparatus and methods of operating such apparatus include iteratively programming a group of memory cells to respective desired data states, wherein a particular memory cell is configured to store overhead data and a different memory cell is configured to store user data; determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, changing the desired data state of the particular memory cell before continuing with the programming. Apparatus and methods of operating such apparatus further include reading a data state of a particular memory cell of a last written page of memory cells, and marking the page as affected by power loss during a programming operation if the particular memory cell has any data state other than a particular data state.

Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.