Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

Abstract: An indication of an initialization of power to a memory device is received. Responsive to receiving the indication of the initialization of power to the memory device, whether a status indicator associated with a written page of the memory device can be read is determined. Responsive to determining that the status indicator cannot be read, a programming of data to the memory device did not complete based on a prior loss of power to the memory device is determined.

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.

Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

Abstract: An indication of an initialization of power to a memory device is received. Responsive to receiving the indication of the initialization of power to the memory device, whether a status indicator associated with a written page of the memory device can be read is determined. Responsive to determining that the status indicator cannot be read, a programming of data to the memory device did not complete based on a prior loss of power to the memory device is determined.

Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.

Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.

Abstract: A processing device reads data from a memory device in response to a received request and performs a first error control operation on the data based on an initial operating characteristic to correct one or more errors in the data. The processing device determines that the first error control operation based on the initial operating characteristic failed to correct the one or more errors in the data, modifies the initial operating characteristic to generate a modified operating characteristic and performs a second error control operation on the data based on the modified operating characteristic to correct the one or more errors in the data.

Abstract: A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.

Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.

Abstract: A total estimated occupancy value of a first data on a first data block of a plurality of data blocks is determined. To determine the total estimated occupancy value of the first data block, a total block power-on-time (POT) value of the first data block is determined. Then, a scaling factor is applied to the total block POT value to determine the total estimated occupancy value of the first data block. Whether the total estimated occupancy value of the first data block satisfies a threshold criterion is determined. Responsive to determining that the total estimated occupancy value of the first data block satisfies the threshold criterion, data stored at the first data block is relocated to a second data block of the plurality of data blocks.

Abstract: A determination can be made that an error control operation associated with user data has failed. An initial operating characteristic associated with the error control operation that failed can be identified. A complementary operating characteristic to replace the operating characteristic associated with the error control operation that failed can be determined. The error control operation for the user data can be performed based on the complementary operating characteristic.