Patents by Inventor Rene Antonio Vega

Rene Antonio Vega has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7987497
    Abstract: Several embodiments of the present invention provide a means for improving data access security in computer systems to support high-security applications, and certain of these embodiments are specifically directed to providing sector-level encryption of a virtual hard disk in a virtual machine environment. More specifically, certain embodiments are directed to providing sector-level encryption by using plug-ins in a virtual machine environment, thereby providing improved data access security in a computer system that supports high-security applications. Certain embodiments also use encryption plug-ins associated with standard encryption software for exchanging data between a virtual machine (VM) and its associated virtual hard drive(s) (VHDs). Moreover, several embodiments of the present invention are directed to the use of plug-in encryption services that interface with, and provide services for, a VM via a VM Encryption API (or its equivalent).
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: July 26, 2011
    Assignee: Microsoft Corporation
    Inventors: Aaron Giles, Eric P. Traut, Rene Antonio Vega
  • Patent number: 7966169
    Abstract: In an emulated computing environment, a method is provided for allocating resources of the host computer system among multiple virtual machines resident on the host computer system. On the basis of the proportional weight of each virtual machine, a proportional share of resources is allocated for each virtual machine. If, for a particular virtual machine, the calculated share is less than a reserved minimum share, the virtual machine is allocated its reserved minimum share as its share of processor resources. An emulation program modulates the access of each virtual machine to the resources of the host computer system.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: June 21, 2011
    Assignee: Microsoft Corporation
    Inventor: Rene Antonio Vega
  • Patent number: 7890951
    Abstract: Model-based provisioning of test environments includes accessing a model of an application to be installed in a test environment of a system and further accessing a model of the system and a model of the test environment. An installation specification for the application is also generated, the installation specification being derived at least in part from the model of the application, the model of the system, and the model of the test environment.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: February 15, 2011
    Assignee: Microsoft Corporation
    Inventors: Anders B. Vinberg, Robert M. Fries, Kevin Grealish, Galen C. Hunt, Aamer Hydrie, Edwin R. Lassettre, Rob Mensching, Geoffrey Outhred, John M. Parchem, Przemek Pardyak, Bassam Tabbara, Rene Antonio Vega, Robert V. Welland, Eric J. Winner, Jeffrey A. Woolsey
  • Publication number: 20100251250
    Abstract: Techniques for implementing a lock-free scheduler with ordering support are described herein. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present disclosure. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects of the present disclosure; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer.
    Type: Application
    Filed: March 30, 2009
    Publication date: September 30, 2010
    Applicant: Microsoft Corporation
    Inventors: Arun U. Kishan, Thomas D. I. Fahrig, Rene Antonio Vega
  • Patent number: 7788464
    Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 31, 2010
    Assignee: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
  • Patent number: 7689747
    Abstract: Various embodiments of the present invention are directed to augmented interrupt controllers (AICs) and to synthetic interrupt sources (SISs) providing richer interrupt information (or “synthetic interrupts” or “SIs”). The AIC and SIS provide efficient means for sending and receiving interrupts, and particularly interrupts sent to and received by virtual machines. Several of these embodiments are specifically directed to an interrupt controller that is extended to accept and deliver additional information associated with an incoming interrupt. For certain such embodiments, a memory-mapped extension to the interrupt controller includes a data structure that is populated with the additional information as part of the interrupt delivery. Although several of the embodiments described herein are disclosed in the context of a virtual machine system, the inventions disclosed herein can also be applied to traditional computer systems (without a virtualization layer) as well.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: March 30, 2010
    Assignee: Microsoft Corporation
    Inventors: Rene Antonio Vega, Nathan T. Lewis
  • Patent number: 7689676
    Abstract: In accordance with certain aspects of the model-based policy application, each of a plurality of policies is associated with appropriate parts of a model of a heterogeneous system. A deployment agent is invoked to apply each of the plurality of policies to components associated with the parts of the model. An identification of a change to one of the plurality of policies is received, and the deployment agent is also invoked to apply the changed policy to selected ones of the components associated with the parts of the model.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: March 30, 2010
    Assignee: Microsoft Corporation
    Inventors: Anders B. Vinberg, Bruce W. Copeland, Robert Fries, Kevin D. J. Grealish, Jonathan C. Hardwick, Michael J. Healy, Galen C. Hunt, Aamer Hydrie, David C. James, Anand Lakshminarayanan, Edwin R. Lassettre, Raymond W. McCollum, Rob Mensching, Mazhar Mohammed, Rajagopalan Badri Narayanan, Geoffrey H. Outhred, Zhengkai Kenneth Pan, Efstathios Papaefstathiou, John M. Parchem, Vij Rajarajan, Ashvinkumar J. Sanghvi, Bassam Tabbara, Rene Antonio Vega, Vitaly Voloshin, Robert V. Welland, John H. Wilson, Eric J. Winner, Jeffrey A. Woolsey
  • Patent number: 7685635
    Abstract: Various embodiments of the present invention are directed to a multi-level virtualizer that is designed to remove much of the intercept-related functionality from the base-level virtualizer (that exists outside of each partition) and, instead, incorporate much of this functionality directly into each partition. For several of the embodiments, certain intercept handling functions are performed by an “external monitor” that runs within a partition and responds to specific intercept events, and the base-level virtualizer installs these external monitors within each partition and thereafter manages the external monitors for both single-partition and cross-partition intercept events. This distributed approach to intercept handling allows for a much less complex virtualizer and moves the intercept functionality up into each partition where each external monitor uses the resources of the corresponding guest operating system in that partition to resolve the intercept event.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: March 23, 2010
    Assignee: Microsoft Corporation
    Inventors: Rene Antonio Vega, Eric P. Traut, Joy Ganguly
  • Publication number: 20100031254
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Applicant: Microsoft Corporation
    Inventors: Yau Ning Chin, Rene Antonio Vega, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig
  • Patent number: 7650482
    Abstract: Enhanced shadow page table algorithms are presented for enhancing typical page table algorithms. In a virtual machine environment, where an operating system may be running within a partition, the operating system maintains it's own guest page tables. These page tables are not the real page tables that map to the real physical memory. Instead, the memory is mapped by shadow page tables maintained by a virtualing program, such as a hypervisor, that virtualizes the partition containing the operating system. Enhanced shadow page table algorithms provide efficient ways to harmonize the shadow page tables and the guest page tables. Specifically, by using tagged translation lookaside buffers, batched shadow page table population, lazy flags, and cross-processor shoot downs, the algorithms make sure that changes in the guest pages tables are reflected in the shadow page tables.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: January 19, 2010
    Assignee: Microsoft Corporation
    Inventors: Eric P. Traut, Matthew D. Hendel, Rene Antonio Vega
  • Patent number: 7580826
    Abstract: The present invention discloses dynamically adding virtual devices to a virtual computing environment. The system described in the invention includes a virtualized computing system with a manifest, which further includes device lists and an external device directory, which provides users of the virtualized computing system with a directory for adding software plug-ins that contain specifications needed to add virtual devices to the virtual computing environment. Certain embodiments are specifically directed to providing a method of adding and configuring virtual devices. Certain embodiments are specifically directed to providing a method of operating a virtualized computing system wherein the host operating system and the virtual devices progress through a series of states, such as: initializing, powering up, loading a stored state, operating in normal state, saving state for future restoration, powering down, and tearing down and turning off.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 25, 2009
    Assignee: Microsoft Corporation
    Inventors: Rene Antonio Vega, Eric P. Traut
  • Patent number: 7533207
    Abstract: Various operations are disclosed for improving the operational efficiency of interrupt handling in a virtualized environment. A virtualized interrupt controller may obviate the need for an explicit end-of-interrupt command by providing an automatic EOI capability even when a physical interrupt controller offers no such mechanism. The use of a message pending bit for inter-partition communications facilitates avoiding an EOI command of inter-processor interrupts used in inter-partition communications whenever no further messages are cued for a particular message slot. A virtualized interrupt controller facilitates the selective EOI of an interrupt even when it is not the highest priority in-service interrupt irrespective of whether a physical interrupt controller provides such functionality.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: May 12, 2009
    Assignee: Microsoft Corporation
    Inventors: Eric P. Traut, Rene Antonio Vega, Shuvabrata Ganguly
  • Patent number: 7434003
    Abstract: An operating system is described that is capable of ascertaining whether it is executing in a virtual machine environment and is further capable of modifying its behavior to operate more efficiently and provide optimal behavior in a virtual machine environment. An operating system is enlightened so that it is aware of VMMs or hypervisors, taking on behavior that is optimal to that environment. The VMM or hypervisor informs the operating system of the optimal behavior, and vice versa.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: October 7, 2008
    Assignee: Microsoft Corporation
    Inventors: Adrian J. Oney, Bryan Mark Willman, Eric P. Traut, Forrest Curtis Foltz, John Te-Jui Sheu, Matthew D. Hendel, Rene Antonio Vega
  • Patent number: 7428626
    Abstract: A method of performing a translation from a guest virtual address to a host physical address in a virtual machine environment includes receiving a guest virtual address from a host computer executing a guest virtual machine program and using the hardware oriented method of the host CPU to determine the guest physical address. A second level address translation to a host physical address is then performed. In one embodiment, a multiple tier tree is traversed which translates the guest physical address into a host physical address. In another embodiment, the second level of address translation is performed by employing a hash function of the guest physical address and a reference to a hash table. One aspect of the invention is the incorporation of access overrides associated with the host physical address which can control the access permissions of the host memory.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: September 23, 2008
    Assignee: Microsoft Corporation
    Inventor: Rene Antonio Vega
  • Publication number: 20080215848
    Abstract: A method of virtualizing memory through shadow page tables that cache translations from multiple guest address spaces in a virtual machine includes a software version of a hardware tagged translation look-aside buffer. Edits to guest page tables are detected by intercepting the creation of guest-writable mappings to guest page tables with translations cached in shadow page tables. The affected cached translations are marked as stale and purged upon an address space switch or an indiscriminate flush of translations by the guest. Thereby, non-stale translations remain cached but stale translations are discarded. The method includes tracking the guest-writable mappings to guest page tables, deferring discovery of such mappings to a guest page table for the first time until a purge of all cached translations when the number of untracked guest page tables exceeds a threshold, and sharing shadow page tables between shadow address spaces and between virtual processors.
    Type: Application
    Filed: April 7, 2008
    Publication date: September 4, 2008
    Inventors: John Te-Jui Sheu, David S. Bailey, Eric P. Traut, Rene Antonio Vega
  • Publication number: 20080155168
    Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Applicant: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
  • Publication number: 20080141277
    Abstract: Various operations are disclosed for improving the operational efficiency of interrupt handling in a virtualized environment. A virtualized interrupt controller may obviate the need for an explicit end-of-interrupt command by providing an automatic EOI capability even when a physical interrupt controller offers no such mechanism. The use of a message pending bit for inter-partition communications facilitates avoiding an EOI command of inter-processor interrupts used in inter-partition communications whenever no further messages are cued for a particular message slot. A virtualized interrupt controller facilitates the selective EOI of an interrupt even when it is not the highest priority in-service interrupt irrespective of whether a physical interrupt controller provides such functionality.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 12, 2008
    Applicant: Microsoft Corporation
    Inventors: Eric P. Traut, Shuvabrata Ganguly, Rene Antonio Vega
  • Publication number: 20080134174
    Abstract: Various operations are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, operations are disclosed that allow for determination of whether present entries in shadow page tables (SPTs) are stale by comparing shadowed guest page table (GPT) entries against snapshots taken when the entries were cached. Other operations are disclosed that allow a virtual machine monitor (VMM) to access shadow page table trees (SPTTs) by walking trees in software or in hardware. Still other operations are disclosed allowing the VMM to use a hash table to relate GVA ranges to SPTs that map them, thus significantly reducing the cost of having to walk each SPTT in order to invalidate desired GVA(s). And, finally, operations are disclosed allowing the VMM to determine global GVA ranges by checking a bitmap, when invalidating global GVAs.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Applicant: Microsoft Corporation
    Inventors: John Te-Jui Sheu, Matthew D. Hendel, Landy Wang, Ernest S. Cohen, Rene Antonio Vega, Sharvil A. Nanavati
  • Publication number: 20080133875
    Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Applicant: Microsoft Corporation
    Inventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
  • Patent number: 7383405
    Abstract: The present invention is a system and method that performs disk migration in a virtual machine environment. The present invention quickly and easily migrates a virtual machine from one host to another thus improving flexibility and efficiency in a virtual machine environment for “load balancing” systems, performing hardware or software upgrades, handling disaster recovery, and so on. Certain of the embodiments are specifically directed to providing a mechanism for migrating the disk state along with the device and memory states, where the disk data resides in a remotely located storage device that is common to multiple host computer systems in a virtual machine environment. The virtual machine migration process, which includes disk data migration, occurs without the user's awareness and, therefore, without the user's experiencing any noticeable interruption.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: June 3, 2008
    Assignee: Microsoft Corporation
    Inventors: Rene Antonio Vega, Eric P. Traut, Mike Neil