Abstract: Disclosed is a debug system that suppresses the supply of extra electrical power for functions disused in the future while maintaining the performance of communication between an electronic control unit and an external unit for development. The debug system includes an electronic control unit that has a microcomputer for controlling the operation of a control target, a transceiver circuit that is capable of communicating data with the microcomputer, and an external unit for development that is capable of rapidly communicating data with the transceiver circuit. The electronic control unit includes a power supply unit for supplying electrical power to the microcomputer. The transceiver circuit operates on electrical power supplied from an external power supply unit, which differs from the power supply unit included in the electronic control unit.

Abstract: The present invention makes it possible to inhibit an MR ratio from decreasing by high-temperature heat treatment in a magnetoresistive effect element using a perpendicular magnetization film. The magnetoresistive effect element includes a data storage layer, a data reference layer, and an MgO film interposed between the data storage layer and the data reference layer. The data storage layer includes a CoFeB film coming into contact with the MgO film, a perpendicular magnetization film, and a Ta film interposed between the CoFeB film and the perpendicular magnetization film. The CoFeB film is magnetically coupled to the perpendicular magnetization film through the Ta film.

Abstract: To provide a clock control circuit, a demodulation device, and a spread spectrum method, which can reduce interference caused by a clock signal on which spread spectrum is performed when demodulating a signal. A clock controller 22 according to the present invention disperses a harmonic of a clock signal in a used frequency band of a reception signal and controls a harmonic remaining in the used frequency band after the dispersion. For example, the clock controller 22 controls an amplitude of the harmonic on the basis of a spread frequency used for the dispersion and a spread width of the harmonic.

Abstract: A circuit including an inverter is provided for a wiring layer. A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract: A control unit of a USB 3.0 device controls the USB 3.0 device that has entered an SS.Disabled state to transition to an Rx.Detect state when a USB 2.0 connection is not established after a predetermined time, in which the USB 2.0 connection is one of an HS (High Speed) connection, an FS (Full Speed) connection, and an LS (Low Speed) connection. This enables quick return to the Rx.Detect state for the USB 3.0 device that entered the SS.Disabled state due to an error in the host.

Abstract: A simulation device and simulation program are provided that can be suitably applied to a manufacturing process including a plurality of processing steps. The simulation device is provided for simulating the manufacturing process including a first processing step using a first mask, and a second processing step using a second mask. The simulation device includes first obtaining means for obtaining a first intensity distribution generated over a substrate of interest for processing by the first mask, second obtaining means for obtaining a second intensity distribution generated over the substrate by the second mask, and revising means for revising an intensity of a region in the first intensity distribution to be processed by the second mask, to a value regarded as a region not to be processed, based on the second intensity distribution.

Abstract: A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

Abstract: To reduce the time of reception operation switching between multiple wireless systems, a semiconductor integrated circuit includes a first reception unit including a first analog reception unit and a first digital reception unit, and a digital interface. The first analog reception unit includes a first reception mixer and a first A/D converter, and the first digital reception unit includes a first digital filter. The first reception unit, an oscillator, and a PLL enable switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second RF reception signal of a second system. In a period of an end transition operation of the first digital reception unit in the switching, the PLL starts a lock operation so as to match a frequency of an oscillation output signal generated from the oscillator to a desired frequency of the second system.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: A light measuring circuit includes an integration circuit for integrating a current supplied form a photoelectric conversion element, an AD converter for AD converting the output voltage of the integration circuit, and a controller for obtaining a first AD conversion result from the AD converter and controlling the integration circuit and the AD converter to determine the time constant of the integration circuit in a second AD conversion following a first AD conversion. In this way, it is possible to measure the photocurrent with a wide dynamic range without making the circuit more complicated.

Abstract: A semiconductor device according to the present invention includes a first module that issues a first transaction from a first interface unit to be a bus master, a second module that includes a second interface unit to be a bus slave and a third interface unit to be a bus master, and issues a second transaction in response to the first transaction, a third module that receives the second transaction by a fourth interface unit to be a bus slave, a bus master stop request control unit that asserts a bus master stop request and completes an assertion process in response to assertion of a bus master stop acknowledgement, and a code addition unit that adds to the first transaction a compulsory process request code for forcing issuance of the second transaction regardless of the bus master stop request.

Abstract: A semiconductor storage device having tunnel magnetoresistive elements in memory cells. The array includes a memory array having a plurality of memory cells; a plurality of read-word-lines and a plurality of write-word-lines; a plurality of read-bit-lines; a plurality of first write-bit-lines and a plurality of second write-bit-lines; a first driver; a read circuit; a second driver; and a write circuit. The memory cell 1 has a mos transistor, one current electrode of which is coupled to the read-bit-line. A tunnel magnetoresistive element is coupled between a control electrode of the mos transistor and the read-word-line. A capacitive element coupled to the tunnel magnetoresistive element MTJ0 forms an RC circuit together with the tunnel magnetoresistive element.

Abstract: There is provided an audio encoding apparatus that can avoid that audio data becomes irreproducible after fast-forward play. A quantization unit quantizes and buffers audio data into a buffer unit. A stream generating unit puts buffered audio data in a frame where there is a header related to the audio data in a stream and/or in one or plural frames preceding that frame. As for a predetermined frame, the stream generating unit puts in a data field of the frame the whole of an audio data piece related to a header included in that frame and puts audio sample data following that audio sample in a remaining part of the data field. As for a frame not a predetermined one, it puts in a data field of the frame an audio data piece related to a header included in that frame and/or audio data pieces following that audio data piece.

Abstract: In power residue calculation in a primality determination, in addition to the conventional randomization of an exponent, a modulus is also randomized. A random number generated by a random number generator is set to a randomizing number, and is input to a modulus generator and an exponent generator. The modulus generator and the exponent generator randomize a prime number candidate P using the randomizing number to generate a randomized modulus R1 and exponent R2. Using the randomized modulus R1 and exponent R2, the power residue calculation for primality determination is executed, and based on the result, the primality of the prime number candidate P is determined. The power consumption during the primality determination of a semiconductor device becomes noncorrelated with a value of a prime number candidate to be determined, and the leakage of a prime number due to side channel attacks can be prevented.

Abstract: A semiconductor device includes a substrate, a transistor formed over the substrate, insulating layers formed over the substrate, a multilayer wiring formed in the insulating layers, a first inductor formed in the insulating layers, and a second inductor formed over the first inductor and overlapping the first inductor. The insulating layers contain a silicon, wherein at least the two insulating layers are formed between the first inductor and the second inductor, and the first inductor and the second inductor are a spiral wiring pattern.

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

Abstract: An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.

Abstract: Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state.

Abstract: In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.