Abstract: A behavioral synthesis method according to the present invention includes generating a scheduled CDFG based on behavioral description information, generating a lifetime for each variable based on the scheduled CDFG, selecting m variables whose lifetimes do not overlap on a time axis, allocating a first register to a first variable having a first bit width and bits of the first bit width within another variable, allocating a second register to bits other than the bits of the first bit width within another variable, and outputting circuit information of a synthesized circuit including the first and second registers.

Abstract: Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.

Abstract: A receiving device according to the present invention includes: a receiver for receiving an OFDM symbol that is modulated by phase shift keying; an FFT processor for applying an FFT process to the received OFDM symbol to obtain a subcarrier signal; a demapping unit for demapping the subcarrier signal to generate a bit string; a norm calculator for calculating the norm of the subcarrier; a weighting factor generator for generating a weighting factor by taking the statistics of the calculated norm; and a weighting unit for obtaining a soft decision value by weighting the bit string after demapping, based on the particular weighting factor. Thus, the receiving device can obtain a soft decision value to achieve good decoding performance with a small number of known signals and processes.

Abstract: A power supply control apparatus includes a first adder configured to generate a difference signal based on a target value and a feedback signal; a compensator having a first transfer function Wc(z) and configured to generate a control signal based on the difference signal; a control target having a second transfer function Wp(z) and configured to output an output signal generated in response to the control signal; a disturbance canceller having a third transfer function {1+Wc(z)·Wp(z)}/{Wc(z)·Wp(z)} and configured to generate a disturbance cancelling signal based on the output signal corresponding to a control amount y; a second adder configured to generate a differential disturbance signal based on an output of the first adder and the disturbance cancelling signal; and a filter circuit which generates the feedback signal based on the differential disturbance signal.

Abstract: A nitride semiconductor layer formed from a nitride semiconductor is provided on at least one surface side of a semiconductor substrate. Impurity regions (a source region, a drain region, and the like) are provided on one surface side in the nitride semiconductor layer and contain an impurity of a first conductivity type. In addition, amorphous regions (a first amorphous region and a second amorphous region) are a part of the impurity regions and are located in a surface layer of the impurity regions. In addition, metallic layers (a source electrode and a drain electrode) come into contact with the amorphous regions (the first amorphous region and the second amorphous region).

Abstract: A semiconductor device includes a first interconnection including a first end, a second interconnection connected to the first interconnection and including a width being gradually wider towards the first end, a third interconnection and a fourth interconnection, the third interconnection and the fourth interconnection being arranged to sandwich the second interconnection. The first interconnection, the second interconnection, the third interconnection, and the fourth interconnection are each formed in a same layer and a width of the first interconnection is wider than a width of the second interconnection.

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract: A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip.

Abstract: A memory system is constituted of a file storage flash memory storing a control program required for a control portion and a large amount of data, and a random access memory storing a program used by the control portion and functioning as a buffer memory for received data. Thus, a memory system for a portable telephone capable of storing a large amount of received data at high-speed and allowing reading of the stored data at high-speed is provided.

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A semiconductor device includes an analog front-end unit that performs analog front-end processing of a measurement signal input from a sensor, where circuit configuration and circuit characteristics for performing the analog front-end processing are changeable, and an MCU unit that converts the measurement signal after the analog front-end processing from analog to digital and sets circuit configuration and circuit characteristics to the analog front-end unit.

Abstract: A semiconductor device includes a wiring board, a semiconductor chip mounted on the wiring board, the semiconductor chip including a bump formation surface, a plurality of first bumps provided within a first region of the bump formation surface, the first bumps being arranged in a first area density, a plurality of second bumps provided within a second region of the bump formation surface, the second bumps being arranged in a second area density, and a plurality of third bumps arranged between the first region and the second region of the bump formation surface in a two-dimensional array. The plurality of third bumps are arranged in a third area density being higher than the second area density and being lower than the first area density.

Abstract: A BGR circuit includes a first bipolar transistor and a second bipolar transistor that are connected between a power supply terminal and a ground terminal, each base of the first bipolar transistor and the second bipolar transistor being connected to an output terminal. A first resistor is connected between the ground terminal and the first bipolar transistor. A second resistor and a third resistor are connected in series between the first resistor and the second bipolar transistor. A temperature correction circuit is connected between the ground terminal and a node between the second resistor and the third resistor, and includes a first transistor having a base connected to an end of the first bipolar transistor of the first resistor. The temperature correction circuit further includes a fourth resistor connected in series to the first transistor.

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

Abstract: Disclosed is a development support apparatus of a semiconductor device that makes it possible to easily develop the semiconductor device, a development support method, and a program product. A design evaluation apparatus is a design evaluation apparatus having an analog front-end unit for inputting a measurement signal of a sensor and an MCU unit, which has a GUI processing unit for displaying a GUI corresponding to a circuit configuration of the analog front-end unit and a register setting unit that generates setting information for setting up the circuit configuration and a circuit characteristic of the analog front-end unit based on an operation of the GUI by a user, and sets the generated setting information in the analog front-end unit through the MCU unit.

Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.

Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Abstract: A DRAM coupled to a system LSI, the DRAM receiving a test pattern from the system LSI to store the test pattern, if a power source of the system LSI is turned on, outputting the stored test pattern to the system LSI, receiving a delay set value from the system LSI, the delay set value being based on the test pattern, storing the delay set value after the power source of the system LSI is turned off and outputting the stored delay set value to the system LSI, if the power source of the system LSI is turned on again.