Patents by Inventor Reza A. Pagaila

Reza A. Pagaila has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160111410
    Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 21, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 9318441
    Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: April 19, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 9263361
    Abstract: A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 16, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Shuangwu Huang, Rajendra D. Pendse
  • Patent number: 9263301
    Abstract: A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor die.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: February 16, 2016
    Assignee: STARS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 9257411
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: February 9, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, JunMo Koo
  • Patent number: 9240380
    Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 19, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon
  • Patent number: 9236352
    Abstract: A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: January 12, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Shuangwu Huang, Nathapong Suthiwongsunthorn, Dioscoro Merilo
  • Patent number: 9236332
    Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: January 12, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, KiYoun Jang, HunTeak Lee
  • Patent number: 9224693
    Abstract: A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: December 29, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Seung Wook Yoon
  • Patent number: 9177901
    Abstract: A semiconductor device has a first semiconductor die mounted to a first contact pad on a leadframe or substrate with bumps. A conductive pillar is formed over a second semiconductor die. The second die is mounted over the first die by electrically connecting the conductive pillar to a second contact pad on the substrate with bumps. The second die is larger than the first die. An encapsulant is deposited over the first and second die. Alternatively, the conductive pillars are formed over the substrate around the first die. A heat sink is formed over the second die, and a thermal interface material is formed between the first and second die. An underfill material is deposited under the first semiconductor die. A shielding layer is formed between the first and second die. An interconnect structure can be formed over the second contact pad of the substrate.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: November 3, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 9153544
    Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.
    Type: Grant
    Filed: March 1, 2014
    Date of Patent: October 6, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Jose A. Caparas, Pandi C. Marimuthu
  • Patent number: 9142431
    Abstract: A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: September 22, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 9142515
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 22, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, DaeSik Choi, Jun Mo Koo
  • Publication number: 20150262977
    Abstract: A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.
    Type: Application
    Filed: June 2, 2015
    Publication date: September 17, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventor: Reza A. Pagaila
  • Publication number: 20150249065
    Abstract: A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.
    Type: Application
    Filed: May 12, 2015
    Publication date: September 3, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Publication number: 20150228628
    Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 13, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 9076803
    Abstract: A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: July 7, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 9064876
    Abstract: A semiconductor device has a substrate with a cavity formed through first and second surfaces of the substrate. A conductive TSV is formed through a first semiconductor die, which is mounted in the cavity. The first semiconductor die may extend above the cavity. An encapsulant is deposited over the substrate and a first surface of the first semiconductor die. A portion of the encapsulant is removed from the first surface of the first semiconductor die to expose the conductive TSV. A second semiconductor die is mounted to the first surface of the first semiconductor die. The second semiconductor die is electrically connected to the conductive TSV. An interposer is disposed between the first semiconductor die and second semiconductor die. A third semiconductor die is mounted over a second surface of the first semiconductor die. A heat sink is formed over a surface of the third semiconductor die.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 23, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Heap Hoe Kuan, Dioscoro A. Merilo
  • Patent number: 9054095
    Abstract: A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: June 9, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 9048211
    Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 2, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua