Patents by Inventor Richard A. Conti
Richard A. Conti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9859212Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: GrantFiled: July 12, 2016Date of Patent: January 2, 2018Assignee: International Business Machines CorporationInventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
-
Patent number: 8673725Abstract: A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.Type: GrantFiled: March 31, 2010Date of Patent: March 18, 2014Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou, Richard A Conti
-
Patent number: 8664102Abstract: A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.Type: GrantFiled: March 31, 2010Date of Patent: March 4, 2014Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou, Richard A Conti
-
Publication number: 20120187522Abstract: A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.Type: ApplicationFiled: January 20, 2011Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael V. Aquilino, Christopher V. Baiocco, Richard A. Conti, Daniel J. Jaeger, Vijay Narayanan
-
Publication number: 20110241085Abstract: A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicants: TOKYO ELECTRON LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou, Richard A. Conti
-
Publication number: 20110241128Abstract: A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicants: TOKYO ELECTRON LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou, Richard A. Conti
-
Patent number: 7998871Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.Type: GrantFiled: June 25, 2008Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Katherina Babich, Todd C. Bailey, Richard A. Conti, Ryan P. Deschner
-
Patent number: 7968270Abstract: A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.Type: GrantFiled: August 25, 2008Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: Marie Angelopoulos, Katherina E. Babich, Sean D. Burns, Richard A. Conti, Allen H. Gabor, Scott D. Halle, Arpan P. Mahorowala, Dirk Pfeiffer
-
Patent number: 7955926Abstract: In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.Type: GrantFiled: March 26, 2008Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Wesley C. Natzle, Renee T. Mo, Rashmi Jha, Kathryn T. Schonenberg, Richard A. Conti
-
Patent number: 7804136Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.Type: GrantFiled: October 19, 2007Date of Patent: September 28, 2010Assignee: International Business Machines CorporationInventors: Richard A. Conti, Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman, Kwong Hon Wong, Daewon Yang
-
Patent number: 7651947Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.Type: GrantFiled: May 25, 2006Date of Patent: January 26, 2010Assignee: International Business Machines CorporationInventors: Katherina Babich, Todd C. Bailey, Richard A. Conti, Ryan P. Deschner
-
Publication number: 20090311855Abstract: A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.Type: ApplicationFiled: August 20, 2009Publication date: December 17, 2009Inventors: Richard A. Bruff, Richard A. Conti, Denise Pendleton-Lipinski, Amanda L. Tessier, Brian L. Tessier, Yun-Yu Wang, Daewon Yang, Chienfan Yu
-
Publication number: 20090243031Abstract: In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.Type: ApplicationFiled: March 26, 2008Publication date: October 1, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wesley C. Natzle, Renee T. Mo, Rashmi Jha, Kathryn T. Schonenberg, Richard A. Conti
-
Publication number: 20090101980Abstract: A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.Type: ApplicationFiled: October 19, 2007Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard A. Bruff, Richard A. Conti, Denise Pendleton-Lipinski, Amanda L. Tessier, Brian L. Tessier, Yun-Yu Wang, Daewon Yang, Chienfan Yu
-
Patent number: 7491660Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.Type: GrantFiled: October 17, 2007Date of Patent: February 17, 2009Assignees: International Business Machines Corporation, Novellus Systems. Inc.Inventors: Richard A. Conti, Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman, Kwong Hon Wong, Daewon Yang
-
Patent number: 7485573Abstract: A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.Type: GrantFiled: February 17, 2006Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Marie Angelopoulos, Katherina E. Babich, Sean D. Burns, Richard A. Conti, Allen H. Gabor, Scott D. Halle, Arpan P. Mahorowala, Dirk Pfeiffer
-
Publication number: 20090004869Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.Type: ApplicationFiled: June 25, 2008Publication date: January 1, 2009Inventors: Katherina Babich, Todd C. Bailey, Richard A. Conti, Ryan P. Deschner
-
Publication number: 20080311508Abstract: A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.Type: ApplicationFiled: August 25, 2008Publication date: December 18, 2008Applicant: INTERNATION BUSINESS MACHINES CORPORATIONInventors: Marie Angelopoulos, Katherina E. Babich, Sean D. Burns, Richard A. Conti, Allen H. Gabor, Scott D. Halle, Arpan P. Mahorowala, Dirk Pfeiffer
-
Patent number: 7462527Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.Type: GrantFiled: July 6, 2005Date of Patent: December 9, 2008Assignees: International Business Machines Corporation, Novellus Systems, Inc.Inventors: Richard A. Conti, Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman, Kwong Hon Wong, Daewon Yang
-
Publication number: 20080286545Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.Type: ApplicationFiled: June 25, 2008Publication date: November 20, 2008Inventors: Katherina Babich, Todd C. Bailey, Richard A. Conti, Ryan P. Deschner