Patents by Inventor Richard A. Conti
Richard A. Conti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7372158Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.Type: GrantFiled: August 28, 2006Date of Patent: May 13, 2008Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Richard A Conti, Chung-Ping Eng, Matthew C Nicholls
-
Publication number: 20080045039Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.Type: ApplicationFiled: October 17, 2007Publication date: February 21, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, NOVELLUS SYSTEMS, INC.Inventors: Richard Conti, Ronald Bourque, Nancy Klymko, Anita Madan, Michael Smits, Roy Tilghman, Kwong Wong, Daewon Yang
-
Publication number: 20080036007Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.Type: ApplicationFiled: October 19, 2007Publication date: February 14, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, NOVELLUS SYSTEMS, INC.Inventors: Richard Conti, Ronald Bourque, Nancy Klymko, Anita Madan, Michael Smits, Roy Tilghman, Kwong Wong, Daewon Yang
-
Patent number: 7326651Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed.Type: GrantFiled: December 14, 2004Date of Patent: February 5, 2008Assignee: International Business Machines CorporationInventors: Heidi Baks, Richard A. Bruff, Richard A. Conti, Allan Upham
-
Publication number: 20070275563Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.Type: ApplicationFiled: May 25, 2006Publication date: November 29, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Katherina Babich, Todd C. Bailey, Richard A. Conti, Ryan P. Deschner
-
Publication number: 20070196748Abstract: A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.Type: ApplicationFiled: February 17, 2006Publication date: August 23, 2007Applicant: International Business Machines CorporationInventors: Marie Angelopoulos, Katherina Babich, Sean Burns, Richard Conti, Allen Gabor, Scott Halle, Arpan Mahorowala, Dirk Pfeiffer
-
Publication number: 20070048981Abstract: A method for protecting a semiconductor device from carbon depletion type damage includes enriching an exposed surface of a porous interlevel dielectric material (ILD) with a carbon based material, and implementing a plasma based operation on the porous ILD material. The enriching of the porous ILD material reduces effects of carbon depletion as a result of the plasma based operation.Type: ApplicationFiled: September 1, 2005Publication date: March 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Richard Conti, Timothy Dalton, Nicholas Fuller, Kelly Malone, Satyanarayana Nitta, Shom Ponoth
-
Patent number: 7179760Abstract: The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.Type: GrantFiled: May 27, 2005Date of Patent: February 20, 2007Assignee: International Buisness Machines CorporationInventors: Richard A. Conti, Thomas F. Houghton, Michael F. Lofaro, Jeffery B. Maxson, Ann H. McDonald, Yun-Yu Wang, Keith Kwong Hon Wong, Daewon Yang
-
Publication number: 20070007548Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.Type: ApplicationFiled: July 6, 2005Publication date: January 11, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, NOVELLUS SYSTEMS INC.Inventors: Richard Conti, Ronald Bourque, Nancy Klymko, Anita Madan, Michael Smits, Roy Tilghman, Kwong Wong, Daewon Yang
-
Publication number: 20070004206Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.Type: ApplicationFiled: August 28, 2006Publication date: January 4, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yun-Yu Wang, Richard Conti, Chung-Ping Eng, Matthew Nicholls
-
Publication number: 20060270245Abstract: The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.Type: ApplicationFiled: May 27, 2005Publication date: November 30, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard Conti, Thomas Houghton, Michael Lofaro, Jeffery Maxson, Ann McDonald, Yun-Yu Wang, Keith Wong, Daewon Yang
-
Patent number: 7138717Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.Type: GrantFiled: December 1, 2004Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Richard A. Conti, Chung-Ping Eng, Matthew C. Nicholls
-
Patent number: 7084079Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.Type: GrantFiled: November 18, 2002Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Richard A. Conti, Daniel C. Edelstein, Gill Yong Lee
-
Publication number: 20060113672Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.Type: ApplicationFiled: December 1, 2004Publication date: June 1, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yun-Yu Wang, Richard Conti, Chung-Ping Eng, Matthew Nicholls
-
Patent number: 6946345Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.Type: GrantFiled: October 17, 2003Date of Patent: September 20, 2005Assignee: International Business Machines CorporationInventors: Jochen Beintner, Wolfgang Bergner, Richard A. Conti, Andreas Knorr, Rolf Weis
-
Publication number: 20050200056Abstract: A fluid depth determination system is provided for a vessel that contains first and second immiscible fluids, where the second fluid floats on top of the first fluid forming an interface therebetween. The system includes a first pressure probe which is located in the floor of the vessel, a second pressure probe being at least vertically moveable in the first and second fluids in a region of the interface, means for collecting pressure readings from the first and second pressure probes and means for calculating the depth of the first fluid based on a difference in the pressure readings. The present invention is also directed to a method of determining a depth of a first fluid having an immiscible second fluid floating on top of the first fluid and forming an interface therebetween.Type: ApplicationFiled: March 11, 2005Publication date: September 15, 2005Inventor: Richard Conti
-
Patent number: 6911378Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.Type: GrantFiled: June 24, 2003Date of Patent: June 28, 2005Assignee: International Business Machines CorporationInventors: Richard A. Conti, Kenneth Davis, John A. Fitzsimmons, David L. Rath, Daewon Yang
-
Publication number: 20050079701Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed.Type: ApplicationFiled: December 14, 2004Publication date: April 14, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Heidi Baks, Richard Bruff, Richard Conti, Allan Upham
-
Publication number: 20040266140Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.Type: ApplicationFiled: June 24, 2003Publication date: December 30, 2004Inventors: Richard A. Conti, Kenneth Davis, John A. Fitzsimmons, David L. Rath, Daewon Yang
-
Publication number: 20040188740Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide.Type: ApplicationFiled: October 17, 2003Publication date: September 30, 2004Applicants: International Business Machines Corp., Infineon Technologies North America Corp.Inventors: Jochen Beintner, Wolfgang Bergner, Richard A. Conti, Andreas Knorr, Rolf Weis