Patents by Inventor Richard A. Gottscho

Richard A. Gottscho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10283325
    Abstract: A processing chamber including multiple plasma sources in a process chamber top. Each one of the plasma sources is a ring plasma source including a primary winding and multiple ferrites. A plasma processing system is also described. A method of plasma processing is also described.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: May 7, 2019
    Assignee: Lam Research Corporation
    Inventors: Ali Shajii, Richard Gottscho, Souheil Benzerrouk, Andrew Cowe, Siddharth P. Nagarkatti, William R. Entley
  • Publication number: 20190094685
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Publication number: 20190049937
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 14, 2019
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Patent number: 10197908
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: February 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Publication number: 20180260509
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Application
    Filed: May 4, 2018
    Publication date: September 13, 2018
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Publication number: 20180240686
    Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 23, 2018
    Inventors: John Patrick Holland, Peter L.G. Ventzek, Harmeet Singh, Richard Gottscho
  • Publication number: 20180228015
    Abstract: A chamber top for a processing chamber is provided. The chamber top includes a first plasma source oriented horizontally over the chamber top and a second plasma source oriented horizontally over the chamber top. The second plasma source is arranged concentrically around the first plasma source. Also included is a first plurality of ferrites encircling the first plasma source and a second plurality of ferrites encircling the second plasma source. A first primary winding is disposed around an outer circumference of the first plasma source and a second primary winding disposed around an outer circumference of the second plasma source. The first and second primary windings pass through the respective plurality of ferrites. A plurality of outlets is disposed on a lower portion of the first and second plasma sources, and the plurality of outlets is oriented between adjacent ones of the first and second plurality of ferrites.
    Type: Application
    Filed: April 10, 2018
    Publication date: August 9, 2018
    Inventors: Ali Shajii, Richard Gottscho, Souheil Benzerrouk, Andrew Cowe, Siddharth P. Nagarkatti, William Entley
  • Patent number: 9996647
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Publication number: 20180144906
    Abstract: A plasma processing method is provided. The method includes receiving a substrate in a substrate support that is configured to be movable along a linear path. The method includes providing at least one process gas into a plasma microchamber. The plasma microchamber is disposed in a processing head having a length that is at least longer than a diameter of the substrate, and said length is perpendicular to said linear path. The method includes generating a plasma in the plasma microchamber by applying power to the plasma microchamber and applying a bias power to the substrate support. The plasma microchamber has an open side process area that is oriented and directed over a surface to be processed, and the open side process area is less than an area of the surface to be processed. The method includes translating said substrate support along said linear path while said microchamber generates the plasma in the plasma microchamber for exposing said plasma over the substrate.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 24, 2018
    Inventors: Richard Gottscho, Rajinder Dhindsa, Mukund Srinivasan
  • Patent number: 9967965
    Abstract: A processing chamber including multiple plasma sources in a process chamber top. Each one of the plasma sources is a ring plasma source including a primary winding and multiple ferrites. A plasma processing system is also described. A method of plasma processing is also described.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: May 8, 2018
    Assignee: Lam Research Corporation
    Inventors: Ali Shajii, Richard Gottscho, Souheil Benzerrouk, Andrew Cowe, Siddharth P. Nagarkatti, William Entley
  • Patent number: 9947557
    Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 17, 2018
    Assignee: Lam Research Corporation
    Inventors: John Patrick Holland, Peter L. G. Ventzek, Harmeet Singh, Richard Gottscho
  • Patent number: 9911578
    Abstract: A plasma deposition chamber is disclosed. A substrate support for supporting a surface to be processed is in the chamber. A processing head including an array of plasma microchambers is also in the chamber. Each of the plasma microchambers includes an open side disposed over at least a first portion of the surface to be processed. The open side has an area less than an entire area of the surface to be processed. A process gas source is coupled to the chamber to provide a process gas the array of plasma microchambers. A radio frequency power supply is connected to at least one electrode of the processing head. The array of plasma microchambers is configured to generate a plasma using the process gas to deposit a layer over the at least first portion of the surface to be processed. A method for performing a plasma deposition is also disclosed.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: March 6, 2018
    Assignee: Lam Research Corporation
    Inventors: Richard Gottscho, Rajinder Dhindsa, Mukund Srinivasan
  • Publication number: 20180004083
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Application
    Filed: August 30, 2017
    Publication date: January 4, 2018
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Publication number: 20170371991
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Application
    Filed: September 7, 2017
    Publication date: December 28, 2017
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Publication number: 20170363950
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Application
    Filed: June 21, 2016
    Publication date: December 21, 2017
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Patent number: 9792393
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: October 17, 2017
    Assignee: Lam Research Corporation
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Patent number: 9778561
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 3, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Publication number: 20170228482
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Application
    Filed: February 8, 2016
    Publication date: August 10, 2017
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Publication number: 20170176983
    Abstract: Disclosed are methods of optimizing a computerized model which relates etched feature profile on a semiconductor device to a set of independent input parameters via the use of a plurality of model parameters. The optimization methods may include modifying the model parameters so that an etch profile generated with the model is such that it reduces a metric indicative of the combined differences between experimental etch profiles resulting from experimental etch processes performed using different sets of values for sets of independent input parameters and computed etch profiles generated from the model and corresponding to the experimental etch profiles. Said metric may be calculated by projecting computed and corresponding experimental etch profiles onto a reduced-dimensional subspace used to calculate a difference between the profiles. Also disclosed herein are systems employing such optimized models, as well as methods of using such models to approximately determine the profile of an etched feature.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Juline Shoeb, Alex Paterson, Richard A. Gottscho
  • Publication number: 20160358754
    Abstract: A plasma source includes a ring plasma chamber, a primary winding around an exterior of the ring plasma chamber, multiple ferrites, wherein the ring plasma chamber passes through each of the ferrites and multiple plasma chamber outlets coupling the plasma chamber to a process chamber. Each one of the plasma chamber outlets having a respective plasma restriction. A system and method for generating a plasma are also described.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Ali Shajii, Richard Gottscho, Souheil Benzerrouk, Andrew Cowe, Siddharth P. Nagarkatti, William R. Entley